參數(shù)資料
型號： MPC8533VTARFB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1067 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-783
文件頁數(shù)： 68/116頁
文件大?。?/td> 1277K
代理商： MPC8533VTARFB
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
55
I
2C
13.2
I2C AC Electrical Specifications
Table 47 provides the AC timing parameters for the I2C interfaces.
Input current each I/O pin (input voltage is between
0.1
× OVDD and 0.9 × OVDD(max)
II
–10
10
μA3
Capacitance for each I/O pin
CI
—10
pF
—
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. Refer to the
MPC8533E PowerQUICC III Integrated Communications Host Processor Reference Manual for information on
the digital filter used.
3. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.
Table 47. I2C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 46).
Parameter
Symbol1
Min
Max
Unit
Notes
SCL clock frequency
fI2C
0400
kHz
—
Low period of the SCL clock
tI2CL
1.3
—
μs—
High period of the SCL clock
tI2CH
0.6
—
μs—
Setup time for a repeated START condition
tI2SVKH
0.6
—
μs—
Hold time (repeated) START condition (after this period,
the first clock pulse is generated)
tI2SXKL
0.6
—
μs—
Data setup time
tI2DVKH
100
—
ns
—
Data hold time:
CBUS compatible masters
I2C bus devices
tI2DXKL
—
0
—
μs2
Data output delay time
tI2OVKL
—0.9
3
Set-up time for STOP condition
tI2PVKH
0.6
—
μs—
Rise time of both SDA and SCL signals
tI2CR
20 + 0.1 Cb
300
ns
4
Fall time of both SDA and SCL signals
tI2CF
20 + 0.1 Cb
300
ns
4
Bus free time between a STOP and START condition
tI2KHDX
1.3
—
μs—
Noise margin at the LOW level for each connected device
(including hysteresis)
VNL
0.1
× OVDD
—V
—
Table 46. I2C DC Electrical Characteristics (continued)
At recommended operating conditions with OVDD of 3.3 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
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