參數(shù)資料
型號： MPC8533VTARFB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1067 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-783
文件頁數(shù)： 36/116頁
文件大小： 1277K
代理商： MPC8533VTARFB
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
26
Freescale Semiconductor
Enhanced Three-Speed Ethernet (eTSEC), MII Management
FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and
source clock in GMII fashion.
When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the
relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn TSECn_TX_CLK,
while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit
clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out
onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is
intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a
source-synchronous timing reference. Typically, the clock edge that launched the data can be used, since
the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. A summary of the
FIFO AC specifications appears in Table 23 and Table 24.
Table 23. FIFO Mode Transmit AC Timing Specification
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Notes
TX_CLK, GTX_CLK clock period
tFIT
—8.0
—
ns
—
TX_CLK, GTX_CLK duty cycle
tFITH
45
50
55
%
—
TX_CLK, GTX_CLK peak-to-peak jitter
tFITJ
——
250
ps
—
Rise time TX_CLK (20%–80%)
tFITR
—
0.75
ns
—
Fall time TX_CLK (80%–20%)
tFITF
—
0.75
ns
—
GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN
hold time
tFITDX
0.5
—
3.0
ns
1
Note:
1. Data valid tFITDV to GTX_CLK Min setup time is a function of clock period and max hold time.
(Min setup = Cycle time – Max hold).
Table 24. FIFO Mode Receive AC Timing Specification
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Notes
RX_CLK clock period
tFIR
—8.0
—
ns
—
RX_CLK duty cycle
tFIRH/tFIRH
45
50
55
%
—
RX_CLK peak-to-peak jitter
tFIRJ
——
250
ps
—
Rise time RX_CLK (20%–80%)
tFIRR
—
0.75
ns
—
Fall time RX_CLK (80%–20%)
tFIRF
—
0.75
ns
—
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
tFIRDV
1.5
—
ns
—
RX_CLK to RXD[7:0], RX_DV, RX_ER hold time
tFIRDX
0.5
—
ns
—
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MPC8533VTARJ 功能描述:微處理器 - MPU PQ38K 8533 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8533VTARJA 功能描述:微處理器 - MPU PQ38K 8533 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8535AVTAKG 功能描述:微處理器 - MPU 8535 COMMERCIAL 600 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8535AVTAKGA 功能描述:微處理器 - MPU 8535 Non E RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8535AVTANG 功能描述:微處理器 - MPU 8535 COMMERCIAL 800 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
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