參數(shù)資料
型號： MPC8533VTANGA
廠商： Freescale Semiconductor
文件頁數(shù)： 31/112頁
文件大?。?/td> 0K
描述： MPU POWERQUICC 783-PBGA
標準包裝： 36
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 800MHz
電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應商設備封裝： 783-FCPBGA（29x29）
包裝： 托盤
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
25
Enhanced Three-Speed Ethernet (eTSEC), MII Management
8.3
FIFO, GMII,MII, TBI, RGMII, RMII, and RTBI AC Timing
Specifications
The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI are presented in this
section.
8.3.1
FIFO AC Specifications
The basis for the AC specifications for the eTSEC FIFO modes is the double data rate RGMII and RTBI
specifications, since they have similar performance and are described in a source-synchronous fashion like
FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and
source clock in GMII fashion.
When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the
relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn TSECn_TX_CLK,
while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit
clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out
onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is
intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a
source-synchronous timing reference. Typically, the clock edge that launched the data can be used, since
the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver.
A summary of the FIFO AC specifications appears in Table 23 and Table 24.
Table 23. FIFO Mode Transmit AC Timing Specification
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Notes
TX_CLK, GTX_CLK clock period
tFIT
—8.0
—
ns
—
TX_CLK, GTX_CLK duty cycle
tFITH
45
50
55
%
—
TX_CLK, GTX_CLK peak-to-peak jitter
tFITJ
——
250
ps
—
Rise time TX_CLK (20%–80%)
tFITR
—
0.75
ns
—
Fall time TX_CLK (80%–20%)
tFITF
—
0.75
ns
—
GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN
hold time
tFITDX
0.5
—
3.0
ns
1
Note:
1. Data valid tFITDV to GTX_CLK Min setup time is a function of clock period and max hold time.
(Min setup = Cycle time – Max hold).
Table 24. FIFO Mode Receive AC Timing Specification
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Notes
RX_CLK clock period
tFIR
—8.0
—
ns
—
RX_CLK duty cycle
tFIRH/tFIRH
45
50
55
%
—
RX_CLK peak-to-peak jitter
tFIRJ
——
250
ps
—
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