參數(shù)資料
型號(hào): MPC8533VTANGA
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 10/112頁(yè)
文件大小: 0K
描述: MPU POWERQUICC 783-PBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 800MHz
電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤(pán)
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
107
System Design Information
Figure 65 shows the JTAG interface connection.
Figure 65. JTAG Interface Connection
HRESET
From Target
Board Sources
COP_HRESET
13
COP_SRESET
SRESET
NC
11
COP_VDD_SENSE2
6
5
15
10
10 k
10 k
COP_CHKSTP_IN
CKSTP_IN
8
COP_TMS
COP_TDO
COP_TDI
COP_TCK
TMS
TDO
TDI
9
1
3
4
COP_TRST
7
16
2
10
12
(if any)
COP
Hea
d
er
14 3
Notes:
3. The KEY location (pin 14) is not physically present on the COP header.
10 k
TRST1
10 k
10 k
10 k
CKSTP_OUT
COP_CHKSTP_OUT
3
13
9
5
1
6
10
15
11
7
16
12
8
4
KEY
No pin
COP Connector
Physical Pinout
1
2
NC
SRESET
2. Populate this with a 10-
resistor for short-circuit/current-limiting protection.
NC
OVDD
10 k
HRESET1
in order to fully control the processor as shown here.
4. Although pin 12 is defined as a No Connect, some debug tools may use pin 12 as an additional GND pin for
1. The COP port and target board should be able to independently assert HRESET and TRST to the processor
improved signal integrity.
TCK
4
5
5. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL
testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be
10 k
6
6. Asserting SRESET causes a machine check interrupt to the e500 core.
A
B
closed to position B.
10 k
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