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參數(shù)資料
| 型號： | MPC852TVR100 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 100 MHz, RISC PROCESSOR, PBGA256 |
| 封裝： | PLASTIC, BGA-256 |
| 文件頁數(shù)： | 12/72頁 |
| 文件大小： | 1210K |
| 代理商： | MPC852TVR100 |
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2
MPC852T Hardware Specifications
MOTOROLA
Features
applications. It particularly excels in Ethernet control applications, including CPE equipment, Ethernet
routers and hubs, VoIP clients, and WiFi access points.
The MPC852T is a PowerPC architecture-based derivative of the Motorola MPC860 Quad Integrated
Communications Controller (PowerQUICC). The CPU on the MPC852T is the MPC8xx core, a 32-bit
microprocessor that implements the PowerPC architecture, incorporating memory management units
(MMUs) and instruction and data caches. The MPC852T is the subset of this family of devices.
2Features
The MPC852T is comprised of three modules that each use the 32-bit internal bus: the MPC8xx core, the
system integration unit (SIU), and the communication processor module (CPM). Figure 1 shows the
MPC852T block diagram.
The following list summarizes the key MPC852T features:
Embedded MPC8xx core up to 100 MHz
Maximum frequency operation of the external bus is 66 MHz
— The 50 MHz / 66 MHz core frequencies support both 1:1 and 2:1 modes.
— The 80 MHz / 100 MHz core frequencies support 2:1 mode only.
Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with 32 32-bit
general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution.
— 4-Kbyte data cache and 4-Kbyte instruction cache
– 4-Kbyte instruction cache is two-way, set-associative with 128 sets.
– 4-Kbyte data cache is two-way, set-associative with 128 sets.
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
cache blocks.
– Caches are physically addressed, implement a least recently used (LRU) replacement
algorithm, and are lockable on a cache block basis.
— MMUs with 32-entry TLB, fully associative instruction, and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
spaces, and 16 protection groups
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank
— Up to 30 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory
devices
— DRAM controller-programmable to support most size and speed memory interfaces
— Four CAS lines, four WE lines, and one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbytes–256 Mbytes)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC852TVR100A | 功能描述:微處理器 - MPU Ethernet 100 MHz RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC852TVR100A | 制造商:Freescale Semiconductor 功能描述:IC COMMUNICATIONS CONTROLLER CMOS BGA |
| MPC852TVR50 | 制造商:Freescale Semiconductor 功能描述: |
| MPC852TVR50A | 功能描述:微處理器 - MPU Ethernet 50 MHz RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC852TVR66 | 功能描述:IC MPU POWERQUICC 66MHZ 256-PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:MPC8xx 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
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