參數(shù)資料
型號(hào)： MPC852TCZT80A
廠商： Freescale Semiconductor
文件頁數(shù)： 56/80頁
文件大小： 0K
描述： IC MPU POWERQUICC 80MHZ 256PBGA
標(biāo)準(zhǔn)包裝： 60
系列： MPC8xx
處理器類型： 32-位 MPC8xx PowerQUICC
速度： 80MHz
電壓： 1.8V
安裝類型： 表面貼裝
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（23x23）
包裝： 托盤
MPC852T PowerQUICC Hardware Specifications, Rev. 4
6
Freescale Semiconductor
Maximum Tolerated Ratings
3
Maximum Tolerated Ratings
This section provides the maximum tolerated voltage and temperature ranges for the MPC852T. Table 1
provides the maximum ratings and operating temperatures.
Figure 2 shows the undershoot and overshoot voltages at the interface of the MPC852T.
Figure 2. Undershoot/Overshoot Voltage for VDDH and VDDL
Table 1. Maximum Tolerated Ratings
Rating
Symbol
Value
Unit
Supply voltage1
1 The power supply of the device must start its ramp from 0.0 V.
VDDL (core voltage)
– 0.3 to 3.4
V
VDDH (I/O voltage)
– 0.3 to 4
V
VDDSYN
– 0.3 to 3.4
V
Difference between VDDL to VDDSYN
100
mV
Input voltage2
2 Functional operating conditions are provided with the DC electrical specifications in Table 5. Absolute maximum ratings are
stress ratings only; functional operation at the maxima is not guaranteed. Stresses beyond those listed may affect device
reliability or cause permanent damage to the device.
Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than VDDH. This restriction applies to power-up and
normal operation (that is, if the MPC852T is unpowered, a voltage greater than 2.5 V must not be applied to its inputs).
Vin
GND – 0.3 to VDDH
V
Storage temperature range
Tstg
– 55 to +150
°C
GND
GND – 0.3 V
GND – 0.7 V
Not to Exceed 10%
VDDH/VDDL + 20%
VDDH/VDDL
VDDH/VDDL + 5%
of tinterface
1
1. tinterface refers to the clock period associated with the bus clock interface.
VIH
VIL
Note:
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