controller, dual I
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� MPC8379EVRALG
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 40/127闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� MPU PWRQUICC II 667MHZ 689TEPBGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� MPC837x PowerQUICC II Pro Processors
瑕栭牷鏂囦欢锛� Introduction to the MPC837x Family
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 27
绯诲垪锛� MPC83xx
铏曠悊鍣ㄩ鍨嬶細 32-浣� MPC83xx PowerQUICC II Pro
閫熷害锛� 667MHz
闆诲锛� 1V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 689-BBGA 瑁搁湶鐒婄洡
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 689-TEPBGA II锛�31x31锛�
鍖呰锛� 鎵樼洡
閰嶇敤锛� MPC8377E-RDBA-ND - BOARD REF DES MPC8377 REV 2.1
MPC8377E-MDS-PB-ND - BOARD MODULAR DEV SYSTEM
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
2
Freescale Semiconductor
controller, dual I2C controllers, a 4-channel DMA controller, an enhanced secured digital host controller,
and a general-purpose I/O port. This figure shows the block diagram of the chip.
Figure 1. MPC8377E Block Diagram and Features
The following features are supported in the chip:
e300c4s core built on Power Architecture technology with 32 KB instruction cache and 32 KB
data cache, a floating point unit, and two integer units
DDR1/DDR2 memory controller supporting a 32/64-bit interface
Peripheral interfaces, such as a 32-bit PCI interface with up to 66-MHz operation
32-bit local bus interface running up to 133-MHz
USB 2.0 (full/high speed) support
Power management controller for low-power consumption
High degree of software compatibility with previous-generation PowerQUICC processor-based
designs for backward compatibility and easier software migration
Optional security engine provides acceleration for control and data plane security protocols
The optional security engine (SEC 3.0) is noted with the extension 鈥淓鈥� at the end. It allows CPU-intensive
cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator
provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms.
MPC8377E
Security
Enhanced
e300 Core
32 KB
I-Cache
32 KB
D-Cache
DUART
Dual I2C
Timers
GPIO
SPI
Interrupt
Controller
DDR1/DDR2
SDRAM
Controller
Local Bus
eTSEC
USB 2.0
Hi-Speed
Host
Device
RGMII, RMII,
RTBI, MII
SATA
PHY
eTSEC
RGMII, RMII,
RTBI, MII
DMA
PCI
x1
x2
PCI
Express
SD/MMC
Controller
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鍙冩暩(sh霉)鎻忚堪
MPC8379EVRALGA 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU 8379 PBGA ST PbFr W/ENC RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324
MPC8379EVRANDA 鍒堕€犲晢:FREESCALE 鍒堕€犲晢鍏ㄧū:Freescale Semiconductor, Inc 鍔熻兘鎻忚堪:PowerQUICC? II Pro Processor Hardware Specifications
MPC8379EVRANFA 鍒堕€犲晢:FREESCALE 鍒堕€犲晢鍏ㄧū:Freescale Semiconductor, Inc 鍔熻兘鎻忚堪:PowerQUICC? II Pro Processor Hardware Specifications
MPC8379EVRANG 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU 837X Encyrpted RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324
MPC8379EVRANGA 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU 8379 PBGA ST PbFr W/ENC RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324