RCWLR[COREPLL] selects" />
參數(shù)資料
型號: MPC8379CVRALGA
廠商: Freescale Semiconductor
文件頁數(shù): 5/117頁
文件大?。?/td> 0K
描述: MPU POWERQUICC II 667MHZ 689PBGA
標(biāo)準(zhǔn)包裝: 27
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 689-TEPBGA II(31x31)
包裝: 托盤
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
102
Freescale Semiconductor
22.2
Core PLL Configuration
RCWLR[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the
e300 core clock (core_clk). Table 76 shows the encodings for RCWLR[COREPLL]. COREPLL values
that are not listed in Table 76 should be considered as reserved.
NOTE
Core VCO frequency = core frequency
× VCO divider
VCO divider has to be set properly so that the core VCO frequency is in the
range of 800–1600 MHz.
Low
0111
7 : 1
175
233
Low
1000
8 : 1
200
267
Low
1001
9 : 1
225
300
Low
1010
10 : 1
250
333
Low
1011
11 : 1
275
367
Low
1100
12 : 1
300
400
Low
1101
13 : 1
325
Low
1110
14 : 1
350
Low
1111
15 : 1
375
Notes:
1. CFG_CLKIN_DIV doubles csb_clk if set high.
2. CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
Table 76. e300 Core PLL Configuration
RCWLR[COREPLL]
core_clk : csb_clk Ratio
VCO Divider 1
0–1
2–5
6
nn
0000
0
PLL bypassed
(PLL off,
csb_clk clocks core directly)
PLL bypassed
(PLL off,
csb_clk clocks core
directly)
11
nnnn
nn/a
n/a
00
0001
01:1
2
01
0001
01:1
4
10
0001
01:1
8
00
0001
11.5:1
2
Table 75. CSB Frequency Options for Agent Mode (continued)
CFG_CLKIN_DIV
at reset1
SPMF
csb_clk :
Input Clock Ratio1
Input Clock Frequency (MHz)2
25
33.33
66.67
csb_clk Frequency (MHz)
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