As described in Section 22, “Clockin" />
參數(shù)資料
型號: MPC8379CVRALGA
廠商: Freescale Semiconductor
文件頁數(shù): 3/117頁
文件大?。?/td> 0K
描述: MPU POWERQUICC II 667MHZ 689PBGA
標準包裝: 27
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤
供應商設(shè)備封裝: 689-TEPBGA II(31x31)
包裝: 托盤
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
100
Freescale Semiconductor
As described in Section 22, “Clocking,The LBIUCM, DDRCM, and SPMF parameters in the reset
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 74
and Table 75 show the expected frequency values for the CSB frequency for select csb_clk to
CLKIN/PCI_SYNC_IN ratios.
The RCWLR[SVCOD] denotes the system PLL VCO internal frequency as shown in Table 73.
Table 72. System PLL Multiplication Factors
RCWLR[SPMF]
System PLL Multiplication Factor
0000
Reserved
0001
Reserved
0010
× 2
0011
× 3
0100
× 4
0101
× 5
0110
× 6
0111–1111
× 7 to × 15
Table 73. System PLL VCO Divider
RCWLR[SVCOD]
VCO Division Factor
00
4
01
8
10
2
11
1
Table 74. CSB Frequency Options for Host Mode
CFG_CLKIN_DIV
SPMF
csb_clk :
Input Clock Ratio1
Input Clock Frequency (MHz)2
25
33.33
66.67
csb_clk Frequency (MHz)
High
0010
2 : 1
133
High
0011
3 : 1
200
High
0100
4 : 1
133
267
High
0101
5 : 1
167
333
High
0110
6 : 1
150
200
400
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