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參數(shù)資料
| 型號： | MPC8377ECVRANGA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689 |
| 封裝： | 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689 |
| 文件頁數(shù)： | 67/124頁 |
| 文件大?。?/td> | 1462K |
| 代理商： | MPC8377ECVRANGA |
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
47
Enhanced Secure Digital Host Controller (eSDHC)
This means that Data + Clock delay must be greater than –2 ns. This is always fulfilled.
11.3
eSDHC AC Timing Specifications (High-Speed Mode)
Table 42 provides the eSDHC AC timing specifications for high-speed mode as defined in Figure 30 and
Table 42. eSDHC AC Timing Specifications for High-Speed Mode
At recommended operating conditions OVDD = 3.3 V ± 165 mV.
Parameter
Symbol1
Min
Max
Unit
Notes
SD_CLK clock frequency—high speed mode
fSHSCK
050
MHz
—
SD_CLK clock cycle
tSFSCK
20
—
ns
—
SD_CLK clock frequency—identification mode
fSIDCK
0400
KHz
—
SD_CLK clock low time
tSHSCKL
7—
ns
SD_CLK clock high time
tSHSCKH
7—
ns
SD_CLK clock rise and fall times
tSHSCKR/
tSHSCKF
—3
ns
Input setup times: SD_CMD, SD_DATx, SD_CD to
SD_CLK
tSHSIVKH
5—
ns
Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK
tSHSIXKH
0—
ns
Output delay time: SD_CLK to SD_CMD, SD_DATx valid
tSHSKHOV
—4
ns
Output Hold time: SD_CLK to SD_CMD, SD_DATx invalid
tSHSKHOX
0—
ns
SD_CLK delay within device
tINT_CLK_DLY
1.5
—
ns
SD Card Input Setup
tISU
6—
ns
SD Card Input Hold
tIH
2—
ns
SD Card Output Valid
tODLY
—14
ns
SD Card Output Hold
tOH
2.5
—
ns
Note:
1 The symbols used for timing specifications herein follow the pattern of t
(first three letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSFSIXKH
symbolizes eSDHC full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K) going
to high (H). Also tSFSKHOV symbolizes eSDHC full speed timing (SFS) for the clock reference (K) to go high (H), with respect
to the output (O) going valid (V) or data output valid time. Note that, in general, the clock reference symbol representation is
based on five letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with
the appropriate letter: R (rise) or F (fall).
2 Measured at capacitive load of 40 pF.
3 For reference only, according to the SD card specifications.
4 Average, for reference only.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8377ECZQAFDA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8377ECZQAFFA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8377ECZQAFGA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8377ECZQAGDA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8377ECZQAGFA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
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