參數(shù)資料
型號: MPC8377E-RDBA
廠商: Freescale Semiconductor
文件頁數(shù): 94/127頁
文件大?。?/td> 0K
描述: BOARD REF DES MPC8377 REV 2.1
設計資源: MPC8379E-RDB Ref Design Guide
標準包裝: 1
系列: PowerQUICC II™ PRO
類型: MPU
適用于相關產(chǎn)品: MPC8377E
所含物品: 板,CD
相關產(chǎn)品: MPC8378EVRANG-ND - MPU PWRQUICC II 800MHZ 689TEPBGA
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MPC8378EVRAGD-ND - MPU PWRQUICC II 400MHZ 689TEPBGA
MPC8379EVRANG-ND - MPU PWRQUICC II 800MHZ 689TEPBGA
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MPC8379EVRAJF-ND - MPU PWRQUICC II 533MHZ 689TEPBGA
MPC8379EVRAGD-ND - MPU PWRQUICC II 400MHZ 689TEPBGA
MPC8377EVRALG-ND - MPU PWRQUICC II 667MHZ 689TEPBGA
MPC8377EVRAJF-ND - MPU PWRQUICC II 533MHZ 689TEPBGA
更多...
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
69
15.5.1
Compliance Test and Measurement Load
The AC timing and voltage parameters must be verified at the measurement point, as specified within
0.2 inches of the package pins, into a test/measurement load shown in Figure 44.
NOTE
The allowance of the measurement point to be within 0.2 inches of the
package pins is meant to acknowledge that package/board routing may
benefit from D+ and D– not being exactly matched in length at the package
pin boundary. If the vendor does not explicitly state where the measurement
point is located, the measurement point is assumed to be the D+ and D–
package pins.
Figure 44. Compliance Test/Measurement Load
16 Serial ATA (SATA)
This section describes the DC and AC electrical specifications for the serial ATA (SATA) of the
MPC8377E. Note that the external cabled applications or long backplane applications (Gen1x and Gen2x)
are not supported.
16.1
Requirements for SATA REF_CLK
The reference clock is a single ended input clock required for the SATA interface operation. The AC
requirements for the SATA reference clock are listed in the Table 54.
Table 54. SATA Reference Clock Input Requirements
Parameter
Condition
Symbol
Min
Typical
Max
Unit
Note
SD_REF_CLK/ SD_REF_CLK
frequency range
—tCLK_REF
100/125/150
MHz
SD_REF_CLK/ SD_REF_CLK
clock frequency tolerance
—tCLK_TOL
–350
0
+350
ppm
SD_REF_CLK/ SD_REF_CLK
reference clock duty cycle
Measured at 1.6V
tCLK_DUTY
40
50
60
%
TX Silicon +
Package
R = 50
Ω
R = 50
Ω
C = CTX
D+ Package Pin
D– Package Pin
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