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參數(shù)資料
| 型號： | MPC8360CZUAJDGA |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 48/102頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU POWERQUICC II PRO 740TBGA |
| 標準包裝： | 21 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 533MHz |
| 電壓： | 1.2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 740-LBGA |
| 供應商設備封裝： | 740-TBGA（37.5x37.5） |
| 包裝： | 托盤 |
| 配用： | MPC8360EA-MDS-PB-ND - KIT APPLICATION DEV 8360 SYSTEM MPC8360E-RDK-ND - BOARD REFERENCE DESIGN FOR MPC |
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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
5
— Eight TDM interfaces on the MPC8360E and four TDM interfaces on the MPC8358E with 1-bit mode for E3/T3
rates in clear channel
— Sixteen independent baud rate generators and 30 input clock pins for supplying clocks to UCC and MCC serial
channels (MCC is only available on the MPC8360E)
— Four independent 16-bit timers that can be interconnected as four 32-bit timers
— Interworking functionality:
–
Layer 2 10/100-Base T Ethernet switch
–
ATM-to-ATM switching (AAL0, 2, 5)
–
Ethernet-to-ATM switching with L3/L4 support
–
PPP interworking
Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP, 802.11i, iSCSI,
and IKE processing. The security engine contains four crypto-channels, a controller, and a set of crypto execution units
(EUs).
— Public key execution unit (PKEU) supporting the following:
–
RSA and Diffie-Hellman
–
Programmable field size up to 2048 bits
–
Elliptic curve cryptography
–
F2m and F(p) modes
–
Programmable field size up to 511 bits
— Data encryption standard execution unit (DEU)
–
DES, 3DES
–
Two key (K1, K2) or three key (K1, K2, K3)
–
ECB and CBC modes for both DES and 3DES
— Advanced encryption standard unit (AESU)
— Implements the Rinjdael symmetric key cipher
— Key lengths of 128, 192, and 256 bits, two key
–
ECB, CBC, CCM, and counter modes
— ARC four execution unit (AFEU)
–
Implements a stream cipher compatible with the RC4 algorithm
–
40- to 128-bit programmable key
— Message digest execution unit (MDEU)
–
SHA with 160-, 224-, or 256-bit message digest
–
MD5 with 128-bit message digest
–
HMAC with either SHA or MD5 algorithm
— Random number generator (RNG)
— Four crypto-channels, each supporting multi-command descriptor chains
–
Static and/or dynamic assignment of crypto-execution units via an integrated controller
–
Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
— Storage/NAS XOR parity generation accelerator for RAID applications
Dual DDR SDRAM memory controllers on the MPC8360E and a single DDR SDRAM memory controller on the
MPC8358E
— Programmable timing supporting both DDR1 and DDR2 SDRAM
— On the MPC8360E, the DDR buses can be configured as two 32-bit buses or one 64-bit bus; on the MPC8358E,
the DDR bus can be configured as a 32- or 64-bit bus
— 32- or 64-bit data interface, up to 333 MHz (for the MPC8360E) and 266 MHz (for the MPC8358E) data rate
— Four banks of memory, each up to 1 Gbyte
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8360CZUAJDHA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications |
| MPC8360CZUAJFGA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications |
| MPC8360CZUAJFHA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications |
| MPC8360CZUALDGA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications |
| MPC8360CZUALDHA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications |
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