Using the PowerQUICC II Pro MPC8358E to Build Small and Medium Enterprise Routers, Rev. 0
Freescale Semiconductor
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Freescale Semiconductor Solutions
Enhanced interworking features is supported on the QUICC Engine to help offload the main CPU with tasks
normally handled in user application software. The QUICC Engine is capable of providing ATM-to-ATM switching
(AAL0, 2, 5), Ethernet-to-ATM switching with L3 / L4 support, and PPP interworking.
The MPC8358E’s security engine allows CPU-intensive cryptographic operations to be offloaded from the main
CPU core. The security-processing accelerator provides hardware acceleration for the DES, 3DES, AES, SHA-1,
MD-5, and ARC-4 algorithms. It includes a public key accelerator and an on-chip random number generator.
The MPC8358E has a single DDR memory controller and both the e300 and QUICC Engine can access this memory
controller.
In summary, the MPC8358E provides SME router vendors with a highly integrated, fully programmable
communications processor that allows reuse of existing legacy PowerQUICC II and III software drivers and
microcode packages. This helps ensure that a low cost system solution can be quickly developed and will offer
flexibility to accommodate new standards and evolving system requirements.
2.1 The PowerQUICC II Pro MPC8358E
The PowerQUICC II Pro MPC8358E is a high performance, highly integrated communication processor solution
that offers the following.
2.1.1 MPC8358E Features
MPC8358E QUICC Engine offers a future proof solution for next generation SME routers by supporting:
programmable protocol termination, hardware interfaces and interworking features to meet evolving
protocol standards.
Independent, integrated, multi-RISC QUICC Engine provides extensive protocol handling, management
and manipulation without host processor intervention thereby freeing the CPU core for higher-level
applications tasks.
Single platform architecture supports the convergence of IP packet networks and ATM networks, including
interworking between them.
Simplified SME Router design with a cost-effective single chip solution for LAN and WAN packet
processing, thus reducing component count, board power consumption, board real estate, lowering costs and
reducing time-to-money.
DDR memory controller—one 64-bit or 2x32-bit interfaces that split data and control plane traffic at up to
333 MHz
e300 PowerPC core (enhanced version of 603e core with 32K bytes of Level 1 Instruction and 32K bytes
of Level 1 Data caches)
32-bit PCI interface
32-bit Local Bus interface
USB
A security engine provides termination or encrypted plane traffic
High degree of software compatibility with previous-generation PowerQUICC processor-based designs for
backward compatibility and easier software migration
Seamless connection to PowerQUICC III family devices for increased control (CPU) application processing
requirements