參數(shù)資料
型號: MPC8349ECZUALDB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 667 MHz, MICROPROCESSOR, PBGA672
封裝: 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, TBGA-672
文件頁數(shù): 5/87頁
文件大小: 1037K
代理商: MPC8349ECZUALDB
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
Freescale Semiconductor
13
RESET Initialization
4.3
TSEC Gigabit Reference Clock Timing
Table 8 provides the TSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications.
5
RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8349EA.
5.1
RESET DC Electrical Characteristics
Table 9 provides the DC electrical characteristics for the RESET pins of the MPC8349EA.
Table 8. EC_GTX_CLK125 AC Timing Specifications
At recommended operating conditions with LVDD = 2.5 ± 0.125 mV/ 3.3 V ± 165 mV
Parameter
Symbol
Min
Typical
Max
Unit
Notes
EC_GTX_CLK125 frequency
tG125
—125
MHz
EC_GTX_CLK125 cycle time
tG125
—8
ns
EC_GTX_CLK rise and fall time
LVDD = 2.5 V
LVDD = 3.3 V
tG125R/tG125F
——
0.75
1.0
ns
1
EC_GTX_CLK125 duty cycle
GMII, TBI
1000Base-T for RGMII, RTBI
tG125H/tG125
45
47
55
53
%2
EC_GTX_CLK125 jitter
±150
ps
2
Notes:
1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for LVDD = 2.5 V and from 0.6 and 2.7 V for
LVDD =3.3 V.
2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. The EC_GTX_CLK125
duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC
GTX_CLK. See Section 8.2.4, “RGMII and RTBI AC Timing Specifications for the duty cycle for 10Base-T and 100Base-T
reference clock.
Table 9. RESET Pins DC Electrical Characteristics1
Parameter
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
—2.0
OVDD +0.3
V
Input low voltage
VIL
—–0.3
0.8
V
Input current
IIN
——
±5
μA
Output high voltage2
VOH
IOH = –8.0 mA
2.4
V
Output low voltage
VOL
IOL = 8.0 mA
0.5
V
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