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參數(shù)資料
| 型號： | MPC8349ECZUAJFB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 38/87頁 |
| 文件大小： | 0K |
| 描述： | IC MPU POWERQUICC II PRO 672TBGA |
| 標準包裝： | 24 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 533MHz |
| 電壓： | 1.2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 672-LBGA |
| 供應商設備封裝： | 672-TBGA（35x35） |
| 包裝： | 托盤 |
| 配用： | MPC8349E-MITX-GP-ND - KIT REFERENCE PLATFORM MPC8349E MPC8349E-MITXE-ND - BOARD REFERENCE FOR MPC8349 MPC8349EA-MDS-PB-ND - KIT MODULAR DEV SYSTEM MPC8349E |
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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
Freescale Semiconductor
43
JTAG
Figure 27 provides the AC test load for TDO and the boundary-scan outputs of the MPC8349EA.
Figure 27. AC Test Load for the JTAG Interface
Figure 28 provides the JTAG clock input timing diagram.
Figure 28. JTAG Clock Input Timing Diagram
Figure 29 provides the TRST timing diagram.
Figure 29. TRST Timing Diagram
JTAG external clock to output high impedance:
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
2
19
9
ns
5, 6
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50
Ω load (see Figure 18).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing
(JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going
to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D)
went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. In general, the clock reference symbol is
based on three letters representing the clock of a particular function. For rise and fall times, the latter convention is used with
the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to tTCLK.
5. Non-JTAG signal output timing with respect to tTCLK.
6. Guaranteed by design and characterization.
Table 41. JTAG AC Timing Specifications (Independent of CLKIN)1 (continued)
At recommended operating conditions (see Table 2).
Parameter
Symbol2
Min
Max
Unit
Notes
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
JTAG
tJTKHKL
tJTGR
External Clock
VM
tJTG
tJTGF
VM = Midpoint Voltage (OVDD/2)
TRST
VM = Midpoint Voltage (OVDD/2)
VM
tTRST
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8349ECZUALDB | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MPC8349ECZUALFB | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MPC8349E-MDS | 功能描述:開發(fā)板和工具包 - 其他處理器 KIT FOR MPC8349E BDS RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MPC8349E-MDS-PB | 功能描述:開發(fā)板和工具包 - 其他處理器 PROCESSR BD MPC8349E RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MPC8349E-MDS-PBE | 功能描述:開發(fā)板和工具包 - 其他處理器 MPC8349E FAMILY ADS RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
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