參數(shù)資料
型號(hào): MPC8343CZQADDB
廠商: Freescale Semiconductor
文件頁數(shù): 44/80頁
文件大?。?/td> 0K
描述: IC MPU PWRQUICC II 620-PBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 266MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 620-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 620-PBGA(29x29)
包裝: 托盤
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
49
Package and Pin Listings
Figure 34 and Figure 35 represent the AC timings from Table 50. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Figure 34 shows the SPI timings in slave mode (external clock).
Figure 34. SPI AC Timing in Slave Mode (External Clock) Diagram
Figure 35 shows the SPI timings in master mode (internal clock).
Figure 35. SPI AC Timing in Master Mode (Internal Clock) Diagram
18 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions. The MPC8343EA is available
18.1
Package Parameters for the MPC8343EA PBGA
The package parameters are as provided in the following list. The package type is 29 mm
× 29 mm,
620 plastic ball grid array (PBGA).
Package outline
29 mm
× 29 mm
Interconnects
620
Pitch
1.00 mm
Module height (maximum)
2.46 mm
SPICLK (Input)
tNEIXKH
tNEIVKH
tNEKHOX
Input Signals:
SPIMOSI
(See Note)
Output Signals:
SPIMISO
(See Note)
Note: The clock edge is selectable on SPI.
SPICLK (Output)
tNIIXKH
tNIKHOX
Input Signals:
SPIMISO
(See Note)
Output Signals:
SPIMOSI
(See Note)
Note: The clock edge is selectable on SPI.
tNIIVKH
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