參數(shù)資料
型號: MPC8343CZQADDB
廠商: Freescale Semiconductor
文件頁數(shù): 43/80頁
文件大?。?/td> 0K
描述: IC MPU PWRQUICC II 620-PBGA
標準包裝: 36
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 266MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 620-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 620-PBGA(29x29)
包裝: 托盤
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
48
Freescale Semiconductor
SPI
17.2
SPI AC Timing Specifications
Table 50 provides the SPI input and output AC timing specifications.
Figure 33 provides the AC test load for the SPI.
Figure 33. SPI AC Test Load
Input current
IIN
——
±5
μA
Output high voltage
VOH
IOH = –8.0 mA
2.4
V
Output low voltage
VOL
IOL = 8.0 mA
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
0.4
V
Table 50. SPI AC Timing Specifications1
Parameter
Symbol2
Min
Max
Unit
SPI outputs valid—Master mode (internal clock) delay
tNIKHOV
—6
ns
SPI outputs hold—Master mode (internal clock) delay
tNIKHOX
0.5
ns
SPI outputs valid—Slave mode (external clock) delay
tNEKHOV
—8
ns
SPI outputs hold—Slave mode (external clock) delay
tNEKHOX
2—
ns
SPI inputs—Master mode (internal clock input setup time
tNIIVKH
4—
ns
SPI inputs—Master mode (internal clock input hold time
tNIIXKH
0—
ns
SPI inputs—Slave mode (external clock) input setup time
tNEIVKH
4—
ns
SPI inputs—Slave mode (external clock) input hold time
tNEIXKH
2—
ns
Notes:
1. Output specifications are measured from the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal.
Timings are measured at the pin.
2. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOX symbolizes the internal timing
(NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).
Table 49. SPI DC Electrical Characteristics (continued)
Parameter
Symbol
Condition
Min
Max
Unit
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
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