- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17046 > MPC8323E-RDB (Freescale Semiconductor)BOARD REFERENCE DESIGN PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC8323E-RDB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 25/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD REFERENCE DESIGN |
| 產(chǎn)品培訓(xùn)模塊： | MPC8323E PowerQUICC II Pro Processor |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PowerQUICC II™ PRO |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | MPC8323E |
| 所含物品： | 參考設(shè)計(jì)板、軟件和說明文檔 |
| 相關(guān)產(chǎn)品： | MPC8323CVRADDC-ND - IC MPU PWRQUICC II 516-PBGA MPC8323CVRAFDC-ND - IC MPU PWRQUICC II 516-PBGA MPC8323CZQADDC-ND - IC MPU PWRQUICC II 516-PBGA MPC8323CZQAFDC-ND - IC MPU PWRQUICC II 516-PBGA MPC8323ECVRAFDC-ND - IC MPU PWRQUICC II 516-PBGA MPC8323ECVRADDC-ND - IC MPU PWRQUICC II 516-PBGA MPC8323ZQAFDC-ND - IC MPU PWRQUICC II 516-PBGA MPC8323ZQADDC-ND - IC MPU PWRQUICC II 516-PBGA MPC8323VRADDC-ND - IC MPU PWRQUICC II 516-PBGA MPC8323EZQAFDC-ND - IC MPU POWERQUICC II 516-PBGA 更多... |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當(dāng)前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
Freescale Semiconductor
31
JTAG
Figure 18 provides the AC test load for TDO and the boundary-scan outputs of the MPC8323E.
Figure 18. AC Test Load for the JTAG Interface
Figure 19 provides the JTAG clock input timing diagram.
Figure 19. JTAG Clock Input Timing Diagram
Figure 20 provides the TRST timing diagram.
Figure 20. TRST Timing Diagram
JTAG external clock to output high impedance:
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
2
19
9
ns
5, 6
6
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-
Ω load (see Figure 14).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device
timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K)
going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals
(D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference
symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the
latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to tTCLK.
5. Non-JTAG signal output timing with respect to tTCLK.
6. Guaranteed by design and characterization.
Table 32. JTAG AC Timing Specifications (Independent of CLKIN)1 (continued)
At recommended operating conditions (see Table 2).
Parameter
Symbol2
Min
Max
Unit
Notes
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
JTAG
tJTKHKL
tJTGR
External Clock
VM
tJTG
tJTGF
VM = Midpoint Voltage (OVDD/2)
TRST
VM = Midpoint Voltage (OVDD/2)
VM
tTRST
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GMC05DRAH-S734 | CONN EDGECARD 10POS .100 R/A SLD |
| RBC13DCST-S288 | CONN EDGECARD 26POS .100 EXTEND |
| STD02W-G | WIRE & CABLE MARKERS |
| STD01W-V | WIRE & CABLE MARKERS |
| 0210490187 | CABLE JUMPER 1.25MM .305M 12POS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8323E-RDB | 制造商:Freescale Semiconductor 功能描述:MPC8323E Integrated Multiservice Gateway |
| MPC8323EVRADDC | 功能描述:微處理器 - MPU 8323 NOPB PBGA W/ENC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8323EVRADDCA | 制造商:Freescale Semiconductor 功能描述:POWERQUICC, 32 BIT POWER ARCHITECTURE SOC, 266MHZ E300, QE, - Trays 制造商:Freescale Semiconductor 功能描述:IC MPU PWRQUICC 266MHZ 516BGA |
| MPC8323EVRAFDC | 功能描述:微處理器 - MPU 8323 NOPB PBGA W/ENC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8323EVRAFDCA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Integrated Communications Processor Family Hardware Specifications |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。