參數(shù)資料
型號(hào): MPC8315E-RDBA
廠商: Freescale Semiconductor
文件頁數(shù): 16/106頁
文件大?。?/td> 0K
描述: BOARD MPU 8315 POWERQUICC II
標(biāo)準(zhǔn)包裝: 1
系列: PowerQUICC II™ PRO
類型: MPU
適用于相關(guān)產(chǎn)品: MPC8315E
所含物品:
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
17
RESET Initialization
6
RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8315E.
6.1
RESET DC Electrical Characteristics
This table provides the DC electrical characteristics for the RESET pins of the MPC8315E.
6.2
RESET AC Electrical Characteristics
This table provides the reset initialization AC timing specifications of the MPC8315E.
Table 8. RESET Pins DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
2.0
NVDD + 0.3
V
Input low voltage
VIL
—–0.3
0.8
V
Input current
IIN
0 V
V
IN NVDD
±5
A
Output high voltage
VOH
IOH = –8.0 mA
2.4
V
Output low voltage
VOL
IOL = 8.0 mA
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
0.4
V
Table 9. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Note
Required assertion time of HRESET to activate reset flow
32
tPCI_SYNC_IN
1
Required assertion time of PORESET with stable clock applied to SYS_CLK_IN
when the device is in PCI host mode
32
tSYS_CLK_IN
2
Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN
when the device is in PCI agent mode
32
tPCI_SYNC_IN
1
HRESET assertion (output)
512
tPCI_SYNC_IN
1
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3] and
CFG_SYS_CLKIN_DIV) with respect to negation of PORESET when the device is
in PCI host mode
4—
tSYS_CLK_IN
2, 4
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3] and
CFG_SYS_CLKIN_DIV) with respect to negation of PORESET when the device is
in PCI agent mode
4—
tPCI_SYNC_IN
1
Input hold time for POR configuration signals with respect to negation of HRESET
0—
ns
Time for the device to turn off POR configuration signals with respect to the
assertion of HRESET
—4
ns
3
Time for the device to turn on POR config signals with respect to the negation of
HRESET
1—
tPCI_SYNC_IN
1, 3
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