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| 型號： | MPC8309CVMAHFCA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 417 MHz, RISC PROCESSOR, PBGA489 |
| 封裝： | 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-489 |
| 文件頁數(shù)： | 8/81頁 |
| 文件大?。?/td> | 484K |
| 代理商： | MPC8309CVMAHFCA |
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MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
16
Freescale Semiconductor
DDR2 SDRAM
The following figure shows the input timing diagram for the DDR controller.
Figure 4. DDR Input Timing Diagram
6.2.2
DDR2 SDRAM Output AC Timing Specifications
The following table provides the output AC timing specifications for the DDR2 SDRAM interfaces.
Table 15. DDR2 SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of 1.8V ± 100mV.
Parameter
Symbol
Min
Max
Unit
Note
Controller skew for MDQS—MDQ/MDM
tCISKEW
ps
1, 2
266 MHz
–750
750
Notes:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
is captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
determined by the equation: tDISKEW = ±(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute
value of tCISKEW.
Table 16. DDR2 SDRAM Output AC Timing Specifications
At recommended operating conditions with GVDD of 1.8V ± 100mV.
Parameter
Symbol1
Min
Max
Unit
Note
MCK cycle time, (MCK/MCK crossing)
tMCK
5.988
8
ns
2
ADDR/CMD output setup with respect to MCK
tDDKHAS
ns
3
333 MHz
266 MHz
2.4
2.5
—
ADDR/CMD output hold with respect to MCK
tDDKHAX
ns
3
333 MHz
266 MHz
2.4
2.5
—
MCK[n]
tMCK
MDQ[x]
MDQS[n]
tDISKEW
D1
D0
tDISKEW
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8309EC | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications |
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