參數(shù)資料
型號： MPC8309CVMAHFCA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 417 MHz, RISC PROCESSOR, PBGA489
封裝： 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-489
文件頁數(shù)： 73/81頁
文件大?。?/td> 484K
代理商： MPC8309CVMAHFCA
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
75
System Design Information
lifetime of the package. Recommended maximum force on the top of the package is 10 lb (4.5 kg) force.
If an adhesive attachment is planned, the adhesive should be intended for attachment to painted or plastic
surfaces and its performance verified under the application requirements.
24.2.1
Experimental Determination of the Junction Temperature with a
Heat Sink
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back calculate the case temperature using a separate measurement of the thermal resistance of the
interface.
From this case temperature, the junction temperature is determined from the junction-to-case thermal
resistance using the following equation:
TJ = TC +(RJC PD)
Eqn. 5
where:
TC = case temperature of the package (C)
RJC = junction-to-case thermal resistance (C/W)
PD = power dissipation (W)
25 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8309.
25.1
System Clocking
The MPC8309 includes three PLLs.
The system PLL (AVDD2) generates the system clock from the externally supplied SYS_CLK_IN
input. The frequency ratio between the system and SYS_CLK_IN is selected using the system PLL
ratio configuration bits as described in Section 23.4, “System PLL Configuration.”
The e300 core PLL (AVDD3) generates the core clock as a slave to the system clock. The frequency
ratio between the e300 core clock and the system clock is selected using the e300 PLL ratio
configuration bits as described in Section 23.5, “Core PLL Configuration.”
The QUICC Engine PLL (AVDD1) which uses the same reference as the system PLL. The QUICC
Engine block generates or uses external sources for all required serial interface clocks.
相關(guān)PDF資料
PDF描述
MPC8313EVRAFF 32-BIT, 333 MHz, MICROPROCESSOR, PBGA516
MPC8313EVRAGD 32-BIT, 400 MHz, MICROPROCESSOR, PBGA516
MPC8313EZQAGDB 32-BIT, 400 MHz, MICROPROCESSOR, PBGA516
MPC8313VRAFF 32-BIT, 333 MHz, MICROPROCESSOR, PBGA516
MPC8313ECZQAGD 32-BIT, 400 MHz, MICROPROCESSOR, PBGA516
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC8309EC 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications
MPC8309-KIT 功能描述:開發(fā)板和工具包 - 其他處理器 For MPC8309 Ethernet USB I2C SPI RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
MPC8309-KIT 制造商:Freescale Semiconductor 功能描述:MPC830x Processor Evaluation Kit
MPC8309-SOM 功能描述:開發(fā)板和工具包 - 其他處理器 For MPC8309 Ethernet USB 16bit 32bit RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
MPC8309VMADDC 制造商:Freescale Semiconductor 功能描述:MPC8309VMADDC - Bulk
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