This table provides the curr" />
參數(shù)資料
型號: MPC8308CZQADD
廠商: Freescale Semiconductor
文件頁數(shù): 3/83頁
文件大?。?/td> 0K
描述: MPU POWERQUICC II PRO 473MAPBGA
標準包裝: 84
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 266MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 473-LFBGA
供應商設備封裝: 473-MAPBGA(19x19)
包裝: 托盤
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Freescale Semiconductor
11
DDR2 SDRAM
This table provides the current draw characteristics for MVREF.
6.2
DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR2 SDRAM interface.
6.2.1
DDR2 SDRAM Input AC Timing Specifications
This table provides input AC timing specifications for the DDR2 SDRAM when GVDD(typ)=1.8 V.
This table provides input AC timing specifications for the DDR2 SDRAM interface.
Table 15. Current Draw Characteristics for MVREF
Parameter / Condition
Symbol
Min
Max
Unit
Note
Current draw for MVREF
IMVREF
500
A1
Note:
1. The voltage regulator for MVREF must be able to supply up to 500 A current.
Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8 V Interface
At recommended operating conditions with GVDD of 1.8 ± 100 mV
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
VIL
—MVREF – 0.45
V
AC input high voltage
VIH
MVREF + 0.45
V
Table 17. DDR2 SDRAM Input AC Timing Specifications
At recommended operating conditions. with GVDD of 1.8± 100 mV
Parameter
Symbol
Min
Max
Unit
Notes
Controller skew for MDQS—MDQ/MECC
266 MHz
tCISKEW
–875
875
ps
1, 2,3
Notes:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is
captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ or MECC signal is called tDISKEW. This can
be determined by the following equation: tDISKEW = +/–(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is
the absolute value of tCISKEW.
3. Memory controller ODT value of 150
is recommended
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