參數(shù)資料
型號： MPC8308CZQADD
廠商： Freescale Semiconductor
文件頁數(shù)： 20/83頁
文件大小： 0K
描述： MPU POWERQUICC II PRO 473MAPBGA
標準包裝： 84
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 266MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 473-LFBGA
供應商設備封裝： 473-MAPBGA（19x19）
包裝： 托盤
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Freescale Semiconductor
27
High-Speed Serial Interfaces (HSSI)
10.2.1
SerDes Reference Clock Receiver Characteristics
Figure 16 shows a receiver reference diagram of the SerDes reference clocks.
The supply voltage requirements for XCOREVDD are specified in Table 1 and Table 2.
SerDes reference clock receiver reference circuit structure
— The SD_REF_CLK and SD_REF_CLK are internally AC-coupled differential inputs as shown
in Figure 16. Each differential clock input (SD_REF_CLK or SD_REF_CLK) has a 50-
termination to XCOREVSS followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the
Differential Mode and Single-ended Mode description below for further detailed requirements.
The maximum average current requirement that also determines the common mode voltage range
— When the SerDes reference clock differential inputs are DC coupled externally with the clock
driver chip, the maximum average current allowed for each input pin is 8mA. In this case, the
exact common mode input voltage is not critical as long as it is within the range allowed by the
maximum average current of 8 mA (refer to the following bullet for more detail), since the
input is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V
(0.4 V/50 = 8 mA) while the minimum common mode input level is 0.1 V above XCOREVSS.
For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output
driven by its current source from 0mA to 16mA (0–0.8 V), such that each phase of the
differential input has a single-ended swing from 0 V to 800 mV with the common mode voltage
at 400mV.
— If the device driving the SD_REF_CLK and SD_REF_CLK inputs cannot drive 50
to
XCOREVSS DC, or it exceeds the maximum input current limitations, then it must be
AC-coupled off-chip.
The input amplitude requirement
— This requirement is described in detail in the following sections.
Figure 16. Receiver of SerDes Reference Clocks
Input
Amp
50
50
SD_REF_CLK
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MPC8308CZQAFD 功能描述:微處理器 - MPU E300 ext tmp Qual333 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
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