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參數(shù)資料
| 型號： | MPC8271CZQTIEA |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 45/61頁 |
| 文件大小： | 0K |
| 描述： | IC MPU POWERQUICC II 516-PBGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | MPC82xx |
| 處理器類型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 400MHz |
| 電壓： | 1.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 516-BBGA |
| 供應(yīng)商設(shè)備封裝： | 516-FPBGA（27x27） |
| 包裝： | 托盤 |
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MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
5
Overview
Integrated security engine (SEC) (MPC8272 and MPC8248 only)
— Supports DES, 3DES, MD-5, SHA-1, AES, PKEU, RNG and RC-4 encryption algorithms
in hardware
Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support
for communications peripherals
— Interfaces to G2_LE core through on-chip dual-port RAM and DMA controller. (Dual-port
RAM size is 16 KB plus 4 KB dedicated instruction RAM.)
— Microcode tracing capabilities
— Eight CPM trap registers
Universal serial bus (USB) controller
— Supports USB 2.0 full/low rate compatible
— USB host mode
– Supports control, bulk, interrupt, and isochronous data transfers
– CRC16 generation and checking
– NRZI encoding/decoding with bit stuffing
– Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and
data rate configuration). Note that low-speed operation requires an external hub.
– Flexible data buffers with multiple buffers per frame
– Supports local loopback mode for diagnostics (12 Mbps only)
— Supports USB slave mode
– Four independent endpoints support control, bulk, interrupt, and isochronous data transfers
– CRC16 generation and checking
– CRC5 checking
– NRZI encoding/decoding with bit stuffing
– 12- or 1.5-Mbps data rate
– Flexible data buffers with multiple buffers per frame
– Automatic retransmission upon transmit error
— Serial DMA channels for receive and transmit on all serial channels
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
— Two fast communication controllers (FCCs) supporting the following protocols:
– 10-/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent
interface (MII)
– Transparent
– HDLC—up to T3 rates (clear channel)
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