Activating data pipelini" />
參數(shù)資料
型號: MPC8271CZQTIEA
廠商: Freescale Semiconductor
文件頁數(shù): 17/61頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II 516-PBGA
標(biāo)準(zhǔn)包裝: 40
系列: MPC82xx
處理器類型: 32-位 MPC82xx PowerQUICC II
速度: 400MHz
電壓: 1.5V
安裝類型: 表面貼裝
封裝/外殼: 516-BBGA
供應(yīng)商設(shè)備封裝: 516-FPBGA(27x27)
包裝: 托盤
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
24
Freescale Semiconductor
AC Electrical Characteristics
NOTE
Activating data pipelining (setting BRx[DR] in the memory controller)
improves the AC timing.
This figure shows the interaction of several bus signals.
Figure 9. Bus Signals
CLKin
AACK/TA/TS/
DATA bus normal mode
All other input signals
PSDVAL/TEA/TA output signals
ADD/ADD_atr/BADDR/CI/
DATA bus output signals
All other output signals
sp11
sp12
sp15
sp10
sp30
sp32
sp33
sp35
DBG/BG/BR input signals
GBL/WT output signals
sp31
input signal
ARTRY/TEA input signals
sp11a
sp10
(except AP)
sp10
sp13
DATA bus pipeline mode
input signal
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