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參數(shù)資料
| 型號(hào)： | MPC8264CZU |
| 廠商： | Motorola, Inc. |
| 英文描述： | MPC826xA (HiP4) Family Hardware Specifications |
| 中文描述： | MPC826xA（HiP4）家庭硬件規(guī)格 |
| 文件頁數(shù)： | 16/48頁 |
| 文件大?。?/td> | 315K |
| 代理商： | MPC8264CZU |
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MPC826xA (HiP4) Family Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
Figure 7 shows TDM input and output signals.
Figure 7. TDM Signal Diagram
Figure 8 shows PIO, timer, and DMA signals.
Figure 8. PIO, Timer, and DMA Signal Diagram
Serial CLKin
TDM input signals
TDM output signals
sp20
sp21
sp40/sp41
Note
: There are four possible TDM timing conditions:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
Sys clk
PIO/IDMA/TIMER[TGATE assertion] input signals
IDMA output signals
sp22
sp23
sp42/sp43
TIMER(sp42/43)/ PIO(sp42a/sp43a)
sp42a/sp43a
output signals
sp42/sp43
TIMER input signal [TGATE deassertion]
sp22
sp23
Note
: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge.
(See note)
(See note)
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