參數(shù)資料
型號(hào)： MPC8264AZUPJDB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 9/50頁(yè)
文件大?。?/td> 0K
描述： IC MPU POWERQUICC II 480-TBGA
標(biāo)準(zhǔn)包裝： 21
系列： MPC82xx
處理器類型： 32-位 MPC82xx PowerQUICC II
速度： 300MHz
電壓： 2V
安裝類型： 表面貼裝
封裝/外殼： 480-LBGA
供應(yīng)商設(shè)備封裝： 408-TBGA（37.5x37.5）
包裝： 托盤
MPC8260A PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2.0
Freescale Semiconductor
17
Electrical and Thermal Characteristics
Figure 6 shows the SCC/SMC/SPI/I2C internal clock.
Figure 6. SCC/SMC/SPI/I2C Internal Clock Diagram
Figure 7 shows TDM input and output signals.
Figure 7. TDM Signal Diagram
BRG_OUT
SCC/SMC/SPI/I2C input signals
SCC/SMC/SPI/I2C output signals
sp18a
sp19a
sp38a/sp39a
(See note.)
Note: There are four possible timing conditions for SCC and SPI:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
Serial CLKin
TDM input signals
TDM output signals
sp20
sp21
sp40/sp41
Note: There are four possible TDM timing conditions:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
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