- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45356 > MPC8260CZUIFBC (MOTOROLA INC) 32-BIT, 200 MHz, RISC PROCESSOR, PBGA480 PDF資料下載
參數(shù)資料
| 型號： | MPC8260CZUIFBC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA480 |
| 封裝： | 37.50 X 37.50 MM, 1.55 MM HEIGHT, 1.27 MM PITCH, TBGA-480 |
| 文件頁數(shù)： | 46/48頁 |
| 文件大?。?/td> | 688K |
| 代理商： | MPC8260CZUIFBC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁當(dāng)前第46頁第47頁第48頁
MOTOROLA
MPC826xA (HiP4) Family Hardware Specications
7
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features
— Supports TC-layer and PMD-WIRE interface (according to the ATM-Forum af-phy-0063.000)
— Cell counters for performance monitoring
– 16-bit counters count
– HEC error cells
– HEC single bit error and corrected cells
– Idle/unassigned cells ltered
– Idle/unassigned cells transmitted
– Transmitted ATM cells
– Received ATM cells
– Maskable interrupt is sent to the host when a counter expires
— Overrun (Rx cell FIFO) and underrun (Tx cell FIFO) condition produces maskable interrupt
— May be operated at E1 and DS-1 rates. In addition, xDSL applications at bit rates up to 10 Mbps
are supported
PCI bridge (MPC8265A and MPC8266A only)
— PCI Specication Revision 2.2 compliant and supports frequencies up to 66 MHz
— On-chip arbitration
— Support for PCI to 60x memory and 60x memory to PCI streaming
— PCI Host Bridge or Periphera
l capabilities
— Includes 4 DMA channels for the following transfers:
– PCI-to-60x to 60x-to-PCI
– 60x-to-PCI to PCI-to-60x
– PCI-to-60x to PCI-to-60x
– 60x-to-PCI to 60x-to-PCI
— Includes all of the conguration registers (which are automatically loaded from the EPROM
and used to congure the MPC8265A) required by the PCI standard as well as message and
doorbell registers
— Supports the I2O standard
— Hot-Swap friendly (supports the Hot Swap Specication as dened by PICMG 2.1 R1.0
August 3, 1998)
— Support for 66 MHz, 3.3 V specication
— 60x-PCI bus core logic which uses a buffer pool to allocate buffers for each port
— Makes use of the local bus signals, so there is no need for additional pins
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC8260ZU200A | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA480 |
| MPC8260CZUIHBC | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA480 |
| MPC8260CZUFFBB3 | 32-BIT, 133 MHz, RISC PROCESSOR, PBGA480 |
| MPC8260ZUIFBC | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA480 |
| MPC8260ZU166A | 32-BIT, 166 MHz, RISC PROCESSOR, PBGA480 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8260EC | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Integrated Communications Processor Hardware Specifications |
| MPC8260VR | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MPC826xA (HiP4) Family Hardware Specifications |
| MPC8260ZU | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MPC826xA (HiP4) Family Hardware Specifications |
| MPC8264 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MPC826xA (HiP4) Family Hardware Specifications |
| MPC8264ACVR | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MPC826xA (HiP4) Family Hardware Specifications |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。