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參數(shù)資料
| 型號： | MPC8260CZUIFBC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA480 |
| 封裝： | 37.50 X 37.50 MM, 1.55 MM HEIGHT, 1.27 MM PITCH, TBGA-480 |
| 文件頁數(shù)： | 11/48頁 |
| 文件大?。?/td> | 688K |
| 代理商： | MPC8260CZUIFBC |
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MOTOROLA
MPC826xA (HiP4) Family Hardware Specications
19
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Clock Conguration Modes
Figure 11. Internal Tick Spacing for Memory Controller Signals
NOTE
The UPM machine outputs change on the internal tick determined by the
memory controller programming; the AC specications are relative to the
internal tick. Note that SDRAM and GPCM machine outputs change on
CLKin’s rising edge.
1.3
Clock Conguration Modes
To congure the main PLL multiplication factor and the core, CPM, and 60x bus frequencies, the
MODCK[1–3] pins are sampled while HRESET is asserted. Table 14 shows the eight basic conguration
modes. Another 49 modes are available by using the conguration pin (RSTCONF) and driving four pins
on the data bus.
1.3.1
Local Bus Mode
Table 14 describes default clock modes for the MPC826xA.
Table 13. Tick Spacing for Memory Controller Signals
PLL Clock Ratio
Tick Spacing (T1 Occurs at the Rising Edge of CLKin)
T2
T3
T4
1:2, 1:3, 1:4, 1:5, 1:6
1/4 CLKin
1/2 CLKin
3/4 CLKin
1:2.5
3/10 CLKin
1/2 CLKin
8/10 CLKin
1:3.5
4/14 CLKin
1/2 CLKin
11/14 CLKin
CLKin
T1
T2
T3
T4
CLKin
T1
T2
T3
T4
for 1:2.5
for 1:3.5
CLKin
T1
T2
T3
T4
for 1:2, 1:3, 1:4, 1:5, 1:6
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