- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄4062 > MPC8245TZU333D (Freescale Semiconductor)IC MPU 32BIT 333MHZ 352-TBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC8245TZU333D |
| 廠(chǎng)商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 32/68頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 333MHZ 352-TBGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | MPC82xx |
| 處理器類(lèi)型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 333MHz |
| 電壓： | 2V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 352-LBGA |
| 供應(yīng)商設(shè)備封裝： | 352-TBGA（35x35） |
| 包裝： | 托盤(pán) |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)當(dāng)前第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
38
Freescale Semiconductor
Package Description
DA[14:15]
F1 J2
Output
GVDD
DRV_MEM_CTRL
2, 6
Notes:
1. Place a pull-up resistor of 120
Ω or less on the TEST0 pin.
2. Treat these pins as no connects (NC) unless debug address functionality is used.
3. This pin has an internal pull-up resistor that is enabled only in the reset state. The value of the internal pull-up resistor is not
guaranteed but is sufficient to ensure that a logic 1 is read into configuration bits during reset if the signal is left unterminated.
4. This pin is a reset configuration pin.
5. DL[0] is a reset configuration pin with an internal pull-up resistor that is enabled only in the reset state. The value of the
internal pull-up resistor is not guaranteed but is sufficient to ensure that a logic 1 is read into configuration bits during reset.
6. Multi-pin signals such as AD[31:0] and MDL[0:31] have their physical package pin numbers listed in an order corresponding
to the signal names. Example: AD0 is on pin C22, AD1 is on pin D22, ..., AD31 is on pin V25.
7. GNT4 is a reset configuration pin with an internal pull-up resistor that is enabled only in the reset state.
8. A weak pull-up resistor (2–10 k
Ω) should be placed on this PCI control pin to LVDD.
10. A weak pull-up resistor (2–10 k
Ω) should be placed on this pin to OVDD.
11. A weak pull-up resistor (2–10 k
Ω) should be placed on this pin to GVDD.
12. This pin has an internal pull-up resistor that is enabled at all times. The value of the internal pull-up resistor is not guaranteed
but is sufficient to prevent unused inputs from floating.
13. An external PCI clocking source or fan-out buffer may be required for the MPC8245 DUART functionality since
PCI_CLK[0:3] are not available in DUART mode. Only PCI_CLK4 is available in DUART mode.
14. This pin is a multiplexed signal and appears more than once in this table.
15. This pin is affected by the programmable PCI_HOLD_DEL parameter.
16. This pin is an open-drain signal.
17. This pin can be programmed as driven (default) or as open-drain (in MIOCR 1).
18. This pin is a sustained three-state pin as defined by the PCI Local Bus Specification.
19. OSC_IN uses the 3.3-V PCI interface driver, which is 5-V tolerant. See Table 2 for details.
20. PLL_CFG signals must be driven on reset and must be held for at least 25 clock cycles after the negation of HRST_CTRL
and HRST_CPU in order to be latched.
21. SDRAM_CLK[0:3] and SDRAM_SYNC_OUT signals use DRV_MEM_CTRL for chip Rev 1.1 (A). These signals use
DRV_MEM_CLK for chip Rev 1.2 (B).
22. The 266- and 300-MHz part offerings can run at a source voltage of 1.8 ± 100 mV or 2.0 ± 100 mV. Source voltage should
be 2.0 ± 100 mV for 333- and 350-MHz parts.
23. This pin is LAVDD on the MPC8240. It is an NC on the MPC8245, which should not pose a problem when an MPC8240 is
replaced with an MPC8245.
24. The driver capability of this pin is hardwired to 40
Ω and cannot be changed.
25. A weak pull-up resistor (2–10 k
Ω) should be placed on this pin to OVDD so that a 1 can be detected at reset if an external
memory clock is not used and PLL[0:4] does not select a half-clock frequency ratio.
26. Typically, the serial port has sufficient drivers in the RS232 transceiver to drive the CTS pin actively as an input. No pullups
are needed in this case.
27. HRST_CPU/HRST_CTRL must transition from a logic 0 to a logic 1 in less than one SDRAM_SYNC_IN clock cycle for the
device to be in the nonreset state
Table 16. MPC8245 Pinout Listing (continued)
Name
Pin Numbers
Type
Power
Supply
Output
Driver Type
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT7005L35PF | IC SRAM 64KBIT 35NS 64TQFP |
| MPC866PVR100A | IC MPU POWERQUICC 100MHZ 357PBGA |
| MPC866PZP100A | IC MPU POWERQUICC 100MHZ 357PBGA |
| MPC823ZQ81B2T | IC MPU 32BIT 81MHZ 256-PBGA |
| 15-47-4050 | CONN FFC FEMALE 5POS .100 GOLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8245TZU350D | 功能描述:微處理器 - MPU 350MHz 665MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線(xiàn)寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8247 | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:MPC8272 PowerQUICC II Family Hardware Specifications |
| MPC8247CVR | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:MPC8272 PowerQUICC II Family Hardware Specifications |
| MPC8247CVRB | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8247CVRE | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。