參數(shù)資料
型號(hào)： MPC8245ARVV400D
廠(chǎng)商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, LEAD FREE, TBGA-352
文件頁(yè)數(shù)： 44/68頁(yè)
文件大小： 1143K
代理商： MPC8245ARVV400D
MPC8245 Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor
49
System Design
reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches,
the COP reset signals must be merged into these signals with logic.
The arrangement shown in Figure 28 allows the COP port to independently assert HRESET or TRST,
while ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not
be used, TRST should be tied to HRESET through a 0-
Ω isolation resistor so that it is asserted when the
system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during
power-on. Although Freescale recommends that the COP header be designed into the system as shown in
Figure 28, if this is not possible, the isolation resistor will allow future access to TRST in the case where
a JTAG interface may need to be wired onto the system in debug situations.
The COP interface has a standard header for connection to the target system based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header). Typically, pin 14 is removed
as a connector key.
There is no standardized way to number the COP header shown in Figure 28. Consequently, different
emulator vendors number the pins differently. Some pins are numbered top-to-bottom and left-to-right
while others use left-to-right then top-to-bottom and still others number the pins counter clockwise from
pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in Figure 28 is
common to all known emulators.
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