參數(shù)資料
型號(hào)： MPC8245ARVV400D
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, LEAD FREE, TBGA-352
文件頁(yè)數(shù)： 20/68頁(yè)
文件大?。?/td> 1143K
代理商： MPC8245ARVV400D
MPC8245 Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor
27
Electrical and Thermal Characteristics
Table 14 provides the I2C output AC timing specifications for the MPC8245 at recommended operating
conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V. Figure 16 through Figure 19 show the I
2C timing
diagrams.
E, F, 32,
33, 34, 35
3072, 3584, 3840,
4096, 5120, 6144
62
95
190
253
10, 11
4608, 5120
42
64
128
170
12, 13, 36,
37, 38, 39
6144, 7168, 7680,
8192, 10240, 12288
31
48
96
128
14, 15
9216, 10240
21
32
64
85
16, 17, 3A,
3B, 3C, 3D
12288, 14336, 15360,
16384, 20480, 24576
16
24
48
64
18, 19
18432, 20480
10
16
32
43
1A, 1B,
3E, 3F
24576, 28672,
30720, 32768
812
24
32
1C, 1D
36864, 40960
5
8
16
21
1E, 1F
49152, 61440
4
6
12
16
Notes:
1. Values are in kHz unless otherwise specified.
2. FDR Hex and Divider (Dec) values are listed in corresponding order.
3. Multiple divider (Dec) values generate the same input frequency, but each divider (Dec) value generates a unique output
frequency as shown in Table 14.
Table 14. I2C Output AC Timing Specifications
Num
Characteristic
Min
Max
Unit
Notes
1
Start condition hold time
(FDR[5] == 0)
× (D
FDR/16)/2N +
(FDR[5] == 1)
× (D
FDR/16)/2M
—
CLKs
1, 2, 3
2
Clock low period
DFDR/2
—
CLKs
1, 2, 3
3
SCL/SDA rise time (from 0.5 to 2.4 V)
—
ms
4
Data hold time
8.0 + (16
× 2FDR[4:2]) × (5 –
4({FDR[5],FDR[1]} == b’10) –
3({FDR[5],FDR[1]} == b’11) –
2({FDR[5],FDR[1]} == b’00) –
1({FDR[5],FDR[1]} == b’01))
—
CLKs
1, 2, 3
5
SCL/SDA fall time (from 2.4 to 0.5 V)
—
< 5
ns
5
6
Clock high time
DFDR/2
—
CLKs
1, 2, 3
Table 13. MPC8245 Maximum I2C Input Frequency (continued)
FDR
Hex 2
Divider 2
(Dec)
Max I2C Input Frequency 1
SDRAM_CLK
@ 33 MHz
SDRAM_CLK
@ 50 MHz
SDRAM_CLK
@ 100 MHz
SDRAM_CLK
@ 133 MHz
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