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參數(shù)資料
| 型號： | MPC8241LZQ266D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA357 |
| 封裝： | 25 X 25 MM, 1.27 MM HEIGHT, PLASTIC, BGA-357 |
| 文件頁數(shù)： | 42/64頁 |
| 文件大小： | 827K |
| 代理商： | MPC8241LZQ266D |
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MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
47
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Design Information
7
System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8241.
7.1 PLL Power Supply Filtering
The AVDD and AVDD2 power signals on the MPC8241 provide power to the peripheral logic/memory bus
PLL and the MPC603e processor PLL. To ensure stability of the internal clocks, the power supplied to the
AVDD and AVDD2 input signals should be filtered of any noise in the 500 kHz to 10 MHz resonant
frequency range of the PLLs. Motorola recommends two separate circuits that are similar to the one shown
in Figure 28 using surface mount capacitors with minimum effective series inductance (ESL) for AVDD and
AVDD2 power signal pins. In High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993)
Dr. Howard Johnson recommends using multiple small capacitors of equal value instead of multiple values.
Place the circuits as close as possible to the respective input signal pins to minimize noise coupled from
nearby circuits. Routing directly as possible from the capacitors to the input signal pins with minimal
inductance of vias is important.
Figure 28. PLL Power Supply Filter Circuit
7.2 Decoupling Recommendations
Dynamic power management, large address and data buses, and high operating frequencies enable the
MPC8241 to generate transient power surges and high frequency noise in its power supply, especially while
driving large capacitive loads. This noise must be prevented from reaching other components in the
MPC8241 system, and the MPC8241 itself requires a clean, tightly regulated source of power. Motorola
recommends that system designers place at least one decoupling capacitor at each VDD, GVDD_OVDD, and
LVDD pin of the MPC8241, and that these decoupling capacitors receive their power from dedicated power
planes in the PCB to utilize short traces to minimize inductance. These capacitors should have a value of
0.1 F. To minimize lead inductance, use only ceramic SMT (surface mount technology) capacitors,
preferably 0508 or 0603, on which connections are made along the length of the part.
In addition, distribute several bulk storage capacitors around the PCB to feed the VDD, GVDD_OVDD, and
LVDD planes and enable quick recharging of the smaller chip capacitors. These bulk capacitors should have
a low ESR (equivalent series resistance) rating to ensure the necessary quick response time, and should be
connected to the power and ground planes through two vias to minimize inductance. Motorola recommends
using bulk capacitors: 100–330 F (AVX TPS tantalum or Sanyo OSCON).
7.3 Connection Recommendations
To ensure reliable operation, Motorola recommends connecting unused inputs to an appropriate signal level.
Unused active-low inputs should be tied to OVDD. Unused active-high inputs should be connected to GND.
All no connect (NC) signals must remain unconnected.
VDD
AVDD or AVDD2
2.2 F
GND
Low ESL Surface Mount Capacitors
10
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