
Memory Controller
MPC561/MPC563 Reference Manual, Rev. 1.2
10-10
Freescale Semiconductor
Figure 10-6. 4 Beat Burst Read with Short Setup Time (Zero Wait State)
NOTE
An extra clock cycle is required to enable short set-up time, resulting in a
4-1-1-1 cycle.
10.3
Chip-Select Timing
The general-purpose chip-select machine (GPCM) allows a glueless and flexible interface between the
MPC561/MPC563 and external SRAM, EPROM, EEPROM, ROM peripherals. When an address and
CLKOUT
ADDR
TS
BR
BG
BB
Data
TA
RD/WR
BURST
TSIZ[0:1]
BDIP
2nd Data 3rd Data
4th Data
is Valid
Last Beat
Expects Another Data
00
ADDR[28:31] = 0000
NO DATA
EXPECTED
12
3
4
5
6
7
1st Data
[0:31]