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參數(shù)資料
| 型號： | MPC564CZP40 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 1323/1420頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT W/CODE COMP 388PBGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | MPC5xx |
| 核心處理器： | PowerPC |
| 芯體尺寸： | 32-位 |
| 速度： | 40MHz |
| 連通性： | CAN，EBI/EMI，SCI，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 56 |
| 程序存儲器容量： | 512KB（512K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.5 V ~ 2.7 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 32x10b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 388-BBGA |
| 包裝： | 托盤 |
| 配用： | MPC564EVB-ND - KIT EVAL FOR MPC561/562/563/564 |
CALRAM Operation
MPC561/MPC563 Reference Manual, Rev. 1.2
22-14
Freescale Semiconductor
Table 22-3. CRAMMCR Bit Descriptions
Bits
Name
Description
0
LCK
Write protection — This bit is designed to lock out writes to the CRAMMCR. While LCK = 0 the
register can be written repeatedly without restriction.
If LCK = 1, the register does not accept writes (i.e., the value of the register remains unchanged,
but the cycle terminates normally.)
In normal mode, this bit can only be set once and can only be cleared by reset.
0 writes to the CRAMMCR are unrestricted
1 writes to the CRAMMCR are ignored
In freeze mode, only the LCK bit may be written to zero if it was previously set.
1
DIS
Array disable — When set, this bit disables the CALRAM array.
In this mode, all reads and writes to the CALRAM array are ignored and a bus error is generated.
The CALRAM responds to register access while DIS = 1.
This is a low power mode for the module, since all internal functions will be disabled.
The module can be re-enabled by writing the DIS bit back to a zero. Reset will also re-enable the
module.
0 CALRAM module array access is enabled
1 CALRAM module array access is disabled
2
2CY
Two cycle mode — When set, this bit puts the CALRAM into a two cycle access mode operation
for CALRAM register accesses as well as array accesses.
This mode provides power savings by using the first cycle to decode any L-bus access for an
address match to where the array resides.
0 CALRAM module in one-cycle operation
1 CALRAM module in two-cycle operation
3:19
—
Reserved
20
R0
Read-only/read-write privilege — If the data relocate (DR) bit is set in Machine Status Register
(MSR in RCPU) and R0 is also set, then write accesses are terminated with an error. If DR bit is
0, both reads and writes to the array block is allowed regardless of the value programmed in R0.
This bit controls the highest 8-Kbyte block (lowest address) of CALRAM in the associated array.
Likewise, R1, R2, and R3 control three other 8-Kbyte blocks in the same manner. See Table 22-4
for control bit address ranges.
R0 = 0 and DR = 0 readable and writable (array 8-Kbyte block)
R0 = 0 and DR = 1 readable and writable (array 8-Kbyte block)
R0 = 1and DR = 0 readable and writable (array 8-Kbyte block)
R0 = 1 and DR = 1 read only (array 8-Kbyte block)
21
D0
Data-only/data-instruction privilege (Data type assignment) — If the data relocate (DR) bit is set
in Machine Status Register (MSR) and D0 is also set, then any access attempting to fetch an
instruction from the array block generates an error. If DR bit is 0, both data read and instruction
fetch from the array block is allowed, regardless of the value programmed in D0.
This bit controls the highest 8-Kbyte block (lowest address) of CALRAM in the associated array.
Likewise, D1, D2, and D3 control three other 8-Kbyte blocks in the same manner. See Table 22-4
for control bit address ranges.
D0 = 0 and DR = 0 data and/or Instruction (array 8-Kbyte block)
D0 = 0 and DR = 1 data and/or Instruction (array 8-Kbyte block)
D0 = 1 and DR = 0 data and/or Instruction (array 8-Kbyte block)
D0 = 1 and DR = 1 data only (array 8-Kbyte block)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC564CZP56 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:RISC MCU Including Peripheral Pin Multiplexing with Flash and Code Compression Options |
| MPC564CZP66 | 功能描述:32位微控制器 - MCU MPC564 512KFLASH Qorivva RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| MPC564EVB | 功能描述:開發(fā)板和工具包 - 其他處理器 DEV BRD W/ETHRNT 10/100TX RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MPC564EVB66 | 制造商:Freescale Semiconductor 功能描述:66MHZ DEV BRD - Bulk |
| MPC564EVBE | 制造商:Freescale Semiconductor 功能描述:DEV BRD W/ETHRNT10 |
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