
Signal Descriptions
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-9
JTAG/BDM/READI
TMS / EVTI
1
I
TMS unless the
Nexus (READI)
port is enabled,
then EVTI.
Test Mode Select. This input controls test mode operations
for on-board test logic (JTAG).
I
EVTI. Event in (EVTI) is level sensitive when configured for
breakpoint generation, otherwise it is edge sensitive.
TDI / DSDI / MDI0
1
I
DSDI unless the
Nexus (READI)
port (MDI0) or
JTAG mode
(TDI) is enabled.
Test Data In. This input is used for serial test instructions
and test data for on-board test logic (JTAG).
I
Development Serial Data Input. This input signal is the data
I
Message Data In. MDI0 is a Nexus input signal used for
downloading configuration information, writes to user
resources, and so forth. Internal latching of MDI occurs on
the rising edge of MCKI.
TCK / DSCK / MCKI
1
I
DSCK unless
the Nexus
(READI) port
(MCKI) or JTAG
mode (TCK) is
enabled.
Test Clock. This input provides a clock for on-board test logic
(JTAG).
I
Development Serial Clock. This input signal is the clock for
I
Message Clock In. This input line is the input clock to the
READI module for the Nexus message clock input.
TDO / DSDO / MDO0
1
O
DSDO unless
the Nexus
(READI) port
(MDO0) or JTAG
mode (TDO) is
enabled.
Test Data Out. This output is used for serial test instructions
and test data for on-board test logic (JTAG).
O
Development Serial Data Output. This output signal is the
data-out line of the debug port interface. See
Chapter 23,O
READI Message Data Out. Message data out: MDO0 is an
output signal used for uploading OTM, BTM, DTM, and
read/write accesses. External latching of MDO occurs on
rising edge of MCKO. Eight MDO signals are implemented.
JCOMP / RSTI
1I
JTAG Compliancy. This signal enables the IEEE1149.1
JTAG compliant circuitry in the MPC561/MPC563.
0JTAG disabled
1 JTAG enabled
IRSTI. Reset input for the Nexus port.
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signal Name
No. of
Signals
Type
Function after
Reset1
Description