
QADC64E Legacy Mode Operation
MPC561/MPC563 Reference Manual, Rev. 1.2
13-66
Freescale Semiconductor
Figure 13-48. Gated Mode, Continuous Scan Timing
13.7
QADC64E Integration Requirements
The QADC64E requires accurate, noise-free input signals for proper operation. This section discusses the
design of external circuitry to maximize QADC64E performance.
The QADC64E uses the external signals shown in
Figure 13-1. There are 16 channel signals that can also
be used as general-purpose digital input signals, 8 of which can be configured as either digital input or
output signals.
13.7.1
Port Digital Input/Output Signals
The 16 port signals on the QADC64E module can be used as analog inputs. Port A signals can be
configured as digital input or digital output signals and Port B signals can be used as 8-bit digital input
signals.
Port A signals are referred to as PQA[7:0] when used as a bidirectional 8-bit digital input/output port.
These eight signals may be used for general-purpose digital input signals or push-pull digital output
signals. Port B signals are referred to as PQB[7:0] when used as digital input signals.
Port A and B signals are connected to a digital input synchronizer during reads and may be used as general
purpose digital inputs when the applied voltages meet high voltage input (VIH) and low voltage input (VIL)
requirements.
Trig1
EOC
QS
CWP
CWPQ1
Q1 RES
0
8
LAST
CCW0
CCW1
R1
CCW3
R3
CF1
TOR1
CCW0
LAST
XX
CCW2
R2
CCW2
CCW1
CCW0
R0
CCW0
CCW3
R3
CCW3
CCW2
R2
CCW3
Q restart
(gate)
Q restart