
Signal Descriptions
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-27
Table 2-11 details the functionality of the ETRIG1/PCS6 and ETRIG2/PCS7 pads dependent on the values
of PDMCR2[PCS6EN], PDMCR2[PCS7EN], SHORT_REG [SH_ET1] and SHORT_REG [SH_ET2].
Also shown in this table is the internal connection of the ETRIG signals when the enhanced chip select
function is used.
0
1
A_T2CLK
PCS4
A_T2CLK/PCS5
Pad
A_T2CLK/PCS5
Pad
1
0
PCS5
B_T2CLK
A_T2CLK Signal
driven HI internally
B_T2CLK/PCS4
Pad
1
0
1
PCS5
B_T2CLK
A_T2CLK Signal
driven HI internally
B_T2CLK Signal
driven HI internally
by connection to
A_T2CLK
1
0
PCS5
PCS4
A_T2CLK Signal
driven HI internally
B_T2CLK Signal
driven HI internally
1
PCS5
PCS4
A_T2CLK Signal
driven HI internally
B_T2CLK Signal
driven HI internally
by connection to
A_T2CLK
1. If PCS4/5EN = 1 then A/B_T2CLK into the module is pulled up internally (enabling Div/8 clock, in gate mode).
2. If only PCS4EN=1, then A_T2CLK can be driven into B_T2CLK if PPM_SHORT[SH_T2CLK] is set.
3. If only PCS5EN=1 then A_T2CLK will be pulled up, if PPM_SHORT[SH_T2CLK] is set, then, B_T2CLK will be high
regardless of pin state.
All of this is regardless of the Pull up/down state.
Note: The PPM shorting function has higher priority logic. If shorting is selected, then A_T2CLK
→ B_T2CLK. If A_T2CLK
is selected as PCS then both A_T2CLK and B_T2CLK will be high regardless of B_T2CLK/PCS4 Pad state.
Table 2-10. Enhanced PCS 4 & 5 Pad Function
PDMCR2
[PCS5EN]
PDMCR2
[PCS4EN]
SHORT_REG
[SH_T2CLK]
A_T2CLK/PCS5
PAD Function
B_T2CLK/PCS4
PAD Function
A_T2CLK internal
TPU_A
Connection
B_T2CLK internal
TPU_B
Connection