Table 12 FMPLL Electrical Characteristics: " />
參數(shù)資料
型號(hào)： MPC5567EVBE
廠商： Freescale Semiconductor
文件頁數(shù)： 60/68頁
文件大?。?/td> 0K
描述： BOARD EVALUATION MPC5567
標(biāo)準(zhǔn)包裝： 1
類型： MCU
適用于相關(guān)產(chǎn)品： MPC5567MZP132
所含物品： 板，線纜，CD，ICD，電源
Revision History for the MPC5567 Data Sheet
MPC5567 Microcontroller Data Sheet, Rev. 2
Freescale
63
Table 12 FMPLL Electrical Characteristics:
Added (TA = TL – TH) to the end of the second line in the table title.
Spec 1, footnote 1 in column 2: ‘PLL reference frequency range’: Changed to read ‘Nominal crystal and external
reference values are worst-case not more than 1%. The device operates correctly if the frequency remains within
± 5% of the specification limit. This tolerance range allows for a slight frequency drift of the crystals over time.
The designer must thoroughly understand the drift margin of the source clock.‘
Spec 1, added two more lines to the PLL reference frequency range’ to read as follows
crystal reference (20)
fref_crystal
8
20
crystal reference (40)
fref_crystal
> 20
40
external reference (20)
fref_ext
8
20
external reference (40)
fref_ext
> 20
40
Spec 1, footnote 2 in column 1: Changed to: ‘The 8–20 MHz crystal or external reference values have PLLCFG[2]
pulled low’ and applies to spec 1, column 2, crystal reference and external reference.
Specs 12 and 13: Grouped (2 x Cl).
Spec 21, column 2: Changed fref_crystal to fref in ICO frequency equation, and
added the same equation but substituted fref_ext for fref for the external reference clock, giving:
fico = [ fref_crystal (MFD + 4) ] (PREDIV + 1)
fico = [ fref_ext (MFD + 4) ] (PREDIV + 1)
Spec 21, column 4, Max: Deleted old footnote 18 that reads:
The ICO frequency can be higher than the maximum allowable system frequency. For this case, set the CMPLL
synthesizer control register reduced frequency divider (FMPLL_SYNCR[RFD]) to divide-by-two (RFD = 0b001).
Therefore, for a 40 MHz maximum device (system frequency), program the FMPLL to generate 80 MHz at the
ICO output and then divide-by-two the RFD to provide the 40 MHz system clock.’
Spec 21: Changed column 5 from ‘fSYS’ MHz’ to: ‘fMAX’.
Spec 22: Changed column 4, Max Value from fMAX to 20, and added footnote 17 to read, ‘Maximum value for
dual controller (1:1) mode is (fMAX 2) and the predivider set to 1 (FMPLL_SYNCR[PREDIV] = 0b001).’
Table 13 eQADC Conversion Specifications: Added (TA = TL – TH) to the table title.
Table 14 Flash Program and Erase Specifications:
Added (TA = TL – TH) to the table title.
Specs 7, 8, 9, and 10 Changed values for the H7Fa Flash pre-program and erase times and used the previous
values for Typical values.
-- 48 KB: from 340 to 345
-- 64 KB: from 400 to 415
Spec 8, 128KB block pre-program and erase time, Max column value from 15,000 to 7,500.
Moved footnote 1 from the table title to directly after the ‘Typical’ in the column 5 header.
Footnote 2: Changed from: ‘Initial factory condition:
100program/erase cycles, 25 oC, typical supply voltage,
80 MHz minimum system frequency.‘ To: ‘Initial factory condition:
100program/erase cycles, 25 oC, using a
typical supply voltage measured at a minimum system frequency of 80 MHz.’
Table 15 Flash EEPROM Module Life:
Replaced (Full Temperature Range) with (TA = TL – TH) in the table title.
Spec 1b, Min. column value changed from 10,000 to 1,000.
Table 35. Table and Figure Changes Between Rev. 0.0 and 1.0 (continued)
Location
Description of Changes
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