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參數(shù)資料
| 型號： | MPC5565MVZ132 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 48/54頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU 2MB FLASH 132MHZ 324-PBGA |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | MPC55xx Qorivva |
| 核心處理器： | e200z6 |
| 芯體尺寸： | 32-位 |
| 速度： | 132MHz |
| 連通性： | CAN，EBI/EMI，SCI，SPI |
| 外圍設(shè)備： | DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 192 |
| 程序存儲器容量： | 2MB（2M x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 80K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.35 V ~ 1.65 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 40x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 324-BBGA |
| 包裝： | 托盤 |
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MPC5565 Microcontroller Data Sheet, Rev. 3
Revision History for the MPC5565 Data Sheet
Freescale Semiconductor
52
5.3
Changes between Revision 0.0 and Revision 1.0
The following table lists the information that changed in the tables between Rev. 0.0 and 1.0.
Specification 1: SCK cycle time. Changed 80 MHz column, Min.: from 25 to 24.4; 112 MHz columns, Min.: from
17.9 to 17.5, Max: from 2.0 to 2.1; 132 MHz columns, Min.: from 15.2 to 14.8, Max: from 1.7 to 1.8.
Footnote 1, changed ‘VDDEH = 3.0–5.5 V;’ to ‘VDDEH = 3.0–5.25 V;’
Table Title: Added footnote that reads: Speed is the nominal maximum frequency. Max speed is the maximum
speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM;
114 MHz parts allow for 112 MHz system clock + 2% FM, 135 MHz parts allow for 132 MHz system clock + 2%
FM.
Table 27 (EQADC SSI Timing Characteristics) EQADC SSI Timing Characteristics
Footnote 1: Changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V.
Table 30. MPC5565 Changes Between Rev. 0.0 and 1.0
Location
Description of Changes
Table 6 (VRC and POR Electrical Specifications) VCR/POR Electrical Specifications:
Added footnote 1 to specs 1, 2, and 3 that reads: On power up, assert RESET before VPOR15, VPOR33, and VPOR5
negate (internal POR). RESET must remain asserted until the power supplies are within the operating conditions
as specified in Table 9 (DC Electrical Specifications (TA = TL to TH)) DC Electrical Specifications. On power down,
assert RESET before any power supplies fall outside the operating conditions and until the internal POR asserts.
Table 9 (DC Electrical Specifications (TA = TL to TH)) DC Electrical Specifications:
Added (TA = TL to TH) to the table title.
Table 22 (Bus Operation Timing) Bus Operation Timing:
External Bus Frequency in the table heading: Added footnote that reads: Speed is the nominal maximum
frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow
for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM, and 135 MHz parts
allow for 132 MHz system clock + 2% FM.
Specifications 5, 6, 7, and 8: Reordered the EBI signals within each specification.
Specs 7 and 8: Removed from external bus interface: BDIP, OE, and WE/BE[0:3].
Footnote 1: Removed VDD = 1.35–1.65 V, and VDD33 and VDDSYN = 3.0–3.6 V.
Table 25 (eMIOS Timing) eMIOS Timing:
Deleted (MTS) from the heading, table, and footnotes.
Footnote 1: Deleted ‘. . .fSYS = 132 MHz. . .’, ‘. . .VDD33 and VDDSYN = 3.0–3.6 V. . .’ and ‘ . . .and CL = 200 pF
with SRC = 0b11.’
Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum
eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad
configuration registers (PCR).’
Table 29. MPC5565 Changes Between Rev. 1.0 and 2.0 (continued)
Location
Description of Changes
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| MPC5565MVZ132R | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller |
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