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| 型號： | MPC5565MVZ132 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 47/54頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU 2MB FLASH 132MHZ 324-PBGA |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | MPC55xx Qorivva |
| 核心處理器： | e200z6 |
| 芯體尺寸： | 32-位 |
| 速度： | 132MHz |
| 連通性： | CAN，EBI/EMI，SCI，SPI |
| 外圍設(shè)備： | DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 192 |
| 程序存儲器容量： | 2MB（2M x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 80K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.35 V ~ 1.65 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 40x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 324-BBGA |
| 包裝： | 托盤 |
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Revision History for the MPC5565 Data Sheet
MPC5565 Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
51
Table 6 (VRC and POR Electrical Specifications) VCR/POR Electrical Specifications:
Added footnote 1 to specs 1, 2, and 3 that reads: The internal POR signals are VPOR15, VPOR33, and VPOR5.
On power up, assert RESET before the internal POR negates. RESET must remain asserted until the power
supplies are within the operating conditions as specified in Table 9 (DC Electrical Specifications (TA = TL to TH))
DC Electrical Specifications. On power down, assert RESET before any power supplies fall outside the operating
conditions and until the internal POR asserts.
Reformatted columns.
Table 9 (DC Electrical Specifications (TA = TL to TH)) DC Electrical Specifications:
Added (TA = TL to TH) to the table title.
Added footnote that reads: VDDE2 and VDDE3 are limited to 2.25–3.6 V only if SIU_ECCR[EBTS] = 0; VDDE2 and
VDDE3 have a range of 1.6–3.6 V if SIU_ECCR[EBTS] =1.
Table 17 (Pad AC Specifications (VDDEH = 5.0 V, VDDE = 1.8 V)) Pad AC Specifications:
Footnote 1, Changed ‘VDDEH = 4.5–5.5;’ to ‘VDDEH = 4.5–5.25;’
Footnote 3, Changed from ‘Out delay. . .’ to ‘The output delay. . .’,
Changed from ‘ Add a maximum of one system clock to the output delay to get the output delay with respect to
the system clock‘to ‘To calculate the output delay with respect to the system clock, add a maximum of one system
clock to the output delay.’
Footnote 4: Changed ‘Delay’ to ‘The output delay.’
Table 19 (Reset and Configuration Pin Timing) Reset and Configuration Pin Timing
Footnote 1: Removed VDD =1.35–1.65.
Table 20 (JTAG Pin AC Electrical Characteristics) JTAG Pin AC Electrical Characteristics
Footnote 1: Removed VDD =1.35–1.65; and VDD33 and VDDSYN = 3.0–3.6 V.
Table 22 (Bus Operation Timing) Bus Operation Timing:
Specifications 5 and 6. Changed EBTS to SIU_ECCR[EBTS].
Specifications 7 and 8: Removed CS[0:3], BDIP, OE, and WE/BE[0:3] because these pins are not used on the
input signal to CLKOUT.
Specification 7: Removed CAL_CS[0, 2:3], CAL_OE, and CAL_WE/BE[0:1] because these pins are not used on
the input signal to CLKOUT.
Specification 8: Added to the beginning of the calibration section: CLKOUT positive edge to input signal invalid
(hold time). Removed CAL_CS[0, 2:3], CAL_OE, and CAL_WE/BE[0:1] because these pins are not used on the
input signal to CLKOUT.
Footnote 1: Deleted VDD = 1.35–1.65; and VDD33 and VDDSYN = 3.0–3.6 V.
Added footnote 2: “Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed
including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow
for 112 MHz system clock + 2% FM; and 135 MHz parts allow for 132 MHz system clock + 2% FM.’
Added footnotes 5, 6, and 7, one each for the DATA[0:31], TEA, and WE/BE[0:3] signals in the table: Due to pin
limitations, the DATA[16:31], TEA, and WE/BE[2:3] signals are not available on the 324 package.
Footnote 8: Changed EBTS to SIU_ECCR[EBTS].
Table 23 (External Interrupt Timing) External Interrupt Timing (IRQ Signals)
Footnote 1: Removed VDD = 1.35–1.65 V; changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V.
Table 24 (eTPU Timing) eTPU Timing
Footnote 1: Changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V.
Table 25 (eMIOS Timing) eMIOS Timing
Footnote 1: Changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V.
Table 26 (DSPI Timing’) DSPI Timing:
Table 29. MPC5565 Changes Between Rev. 1.0 and 2.0 (continued)
Location
Description of Changes
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