參數(shù)資料
型號(hào): MPC5510KIT144
廠商: Freescale Semiconductor
文件頁數(shù): 42/54頁
文件大小: 0K
描述: KIT DEVELOPMENT FOR MPC5
標(biāo)準(zhǔn)包裝: 1
系列: Qorivva
類型: MCU
適用于相關(guān)產(chǎn)品: MPC5510
所含物品:
Electrical Characteristics
MPC5510 Microcontroller Family Data Sheet, Rev. 3
Freescale Semiconductor
47
2.13.7
Deserial Serial Peripheral Interface (DSPI)
Table 25. DSPI Timing1
1 DSPI timing specified at VDDE = 3.0V to 5.5V, T
A = TL to TH, and CL = 50pF with SRC = 0b11.
Num
Characteristic
Symbol
66 MHz
Unit
Min
Max
1
SCK Cycle TIme2,3
2 The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated
based on two MPC55xx devices communicating over a DSPI link.
3 The actual minimum SCK Cycle Time is limited by pad performance.
tSCK
60
ns
2
PCS to SCK Delay4
4 The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]
tCSC
20
ns
3
After SCK Delay5
5 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]
tASC
20
ns
4
SCK Duty Cycle
tSDC
tSCK/2
–2ns
tSCK/2
+ 2ns
ns
5Slave Access Time
(SS active to SOUT driven)
tA
25
ns
6
Slave SOUT Disable Time
(SS inactive to SOUT High-Z or invalid)
tDIS
25
ns
7
PCSx to PCSS time
tPCSC
4—
ns
8PCSS to PCSx time
tPASC
5—
ns
9
Data Setup Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)6
Master (MTFE = 1, CPHA = 1)
6 This number is calculated assuming the SMPL_PT bit field in DSPI_MCR is set to 0b10.
tSUI
35
5
35
ns
10
Data Hold Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)6
Master (MTFE = 1, CPHA = 1)
tHI
–4
10
26
–4
ns
11
Data Valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA=0)
Master (MTFE = 1, CPHA=1)
tSUO
15
35
30
15
ns
12
Data Hold Time for Outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
tHO
–15
5.5
0
–15
ns
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