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參數(shù)資料
| 型號(hào)： | MPC5200VR400B |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 63/72頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MPU PROCESSOR 32BIT 272-PBGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | MPC52xx |
| 核心處理器： | e300 |
| 芯體尺寸： | 32-位 |
| 速度： | 400MHz |
| 連通性： | CAN，EBI/EMI，以太網(wǎng)，I²C，IrDA，J1850，SPI，UART/USART，USB |
| 外圍設(shè)備： | AC'97，DMA，I²S，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 56 |
| 程序存儲(chǔ)器類型： | 外部程序存儲(chǔ)器 |
| RAM 容量： | 16K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.42 V ~ 1.58 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 272-BBGA |
| 包裝： | 托盤 |
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MPC5200B Data Sheet, Rev. 4
66
Freescale Semiconductor
3.3.2
Pull-up Requirements for the PCI Control Lines
If the PCI interface is NOT used (and internally disabled) the PCI control pins must be terminated as indicated by the PCI Local
Bus specification. This is also required for MOST/Graphics and Large Flash Mode.
PCI control signals always require pull-up resistors on the motherboard (not the expansion board) to ensure that they contain
stable values when no agent is actively driving the bus. This includes PCI_FRAME, PCI_TRDY, PCI_IRDY, PCI_DEVSEL,
PCI_STOP, PCI_SERR, PCI_PERR, and PCI_REQ.
3.3.3
Pull-up/Pull-down Requirements for MEM_MDQS Pins (SDRAM)
The MEM_MDQS[3:0] signals are not used with SDR memories and require pull-up or pull-down resistors in SDRAM mode.
3.3.4
.
Pull-up/Pull-down Requirements for MEM_MDQS Pins (DDR 16-bit
Mode)
The MEM_MDQS[1:0] signals are not used in DDR 16-bit mode and require pull-down resistors.
3.4
JTAG
The MPC5200B provides the user an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also provides a Common
On-Chip Processor (COP) Interface, which shares the IEEE 1149.1 JTAG port. The COP Interface provides access to the
MPC5200B's embedded Freescale (formerly Motorola) MPC603e e300 processor. This interface provides a means for
executing test routines and for performing software development and debug functions.
3.4.1
JTAG_TRST
Boundary scan testing is enabled through the JTAG interface signals. The JTAG_TRST signal is optional in the IEEE 1149.1
specification but is provided on all processors that implement the PowerPC architecture. To obtain a reliable power-on reset
performance, the JTAG_TRST signal must be asserted during power-on reset.
3.4.1.1
JTAG_TRST and PORRESET
The JTAG interface can control the direction of the MPC5200B I/O pads via the boundary scan chain. The JTAG module must
be reset before the MPC5200B comes out of power-on reset; do this by asserting JTAG_TRST before PORRESET is released.
For more details refer to the Reset and JTAG Timing Specification.
Figure 53. PORRESET vs. JTAG_TRST
3.4.1.2
Connecting JTAG_TRST
The wiring of the JTAG_TRST depends on the existence of a board-related debug interface. (see below)
JTAG_TRST
PORRESET
Required assertion of JTAG_TRST
Optional assertion of JTAG_TRST
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| MPC5200VR400BR2 | 功能描述:IC MPU 32BIT 400MHZ 272-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MPC52xx 標(biāo)準(zhǔn)包裝:1 系列:AVR® ATmega 核心處理器:AVR 芯體尺寸:8-位 速度:16MHz 連通性:I²C，SPI，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，POR，PWM，WDT 輸入/輸出數(shù):32 程序存儲(chǔ)器容量:32KB（16K x 16） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:1K x 8 RAM 容量:2K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:44-TQFP 包裝:剪切帶 (CT) 其它名稱:ATMEGA324P-B15AZCT |
| MPC52100J | 功能描述:厚膜電阻器 - 透孔 RoHS:否 制造商:Caddock 電阻:27 kOhms 容差:1 % 功率額定值:8 W 溫度系數(shù):50 PPM / C 系列:MS 端接類型:Axial 電壓額定值:2 kV 工作溫度范圍:- 15 C to + 275 C 尺寸:8.89 mm Dia. x 23.11 mm L 封裝:Bulk |
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| MPC52100J | 制造商:TE Connectivity 功能描述:RESISTOR THICK FILM 10OHM 5W 5% 制造商:TE Connectivity 功能描述:RESISTOR, THICK FILM, 10 OHM, 5W, 5% |
| MPC52101J | 功能描述:厚膜電阻器 - 透孔 MPC5 100R 5% RoHS:否 制造商:Caddock 電阻:27 kOhms 容差:1 % 功率額定值:8 W 溫度系數(shù):50 PPM / C 系列:MS 端接類型:Axial 電壓額定值:2 kV 工作溫度范圍:- 15 C to + 275 C 尺寸:8.89 mm Dia. x 23.11 mm L 封裝:Bulk |
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