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| 型號： | MPC5200ID |
| 廠商： | Motorola, Inc. |
| 英文描述： | MPC5200 Hardware Specifications |
| 中文描述： | MPC5200的硬件規(guī)格 |
| 文件頁數(shù)： | 30/76頁 |
| 文件大?。?/td> | 1404K |
| 代理商： | MPC5200ID |
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MPC5200 Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
3.3.8 ATA
The MPC5200 ATA Controller is completely software programmable. It can be programmed to operate with
ATA protocols using their respective timing, as described in the ANSI ATA-4 specification. The ATA
interface is completely asynchronous in nature. Signal relationships are based on specific fixed timing in
terms of timing units (nano seconds).
ATA data setup and hold times, with respect to Read/Write strobes, are software programmable inside the
ATA Controller. Data setup and hold times are implemented using counters. The counters count the
number of ATA clock cycles needed to meet the ANSI ATA-4 timing specifications. For details, see the
ANSI ATA-4 specification [5] and how to program an ATA Controller and ATA drive for different ATA
protocols and their respective timing. See the MPC5200 User Manual
[1].
The MPC5200 ATA Host Controller design makes data available coincidentally with the active edge of the
WRITE strobe in PIO and Multiword DMA modes.
Write data is latched by the drive at the inactive edge of the WRITE strobe. This gives ample
setup-time beyond that required by the ATA-4 specification.
Data is held unchanged until the next active edge of the WRITE strobe. This gives ample hold-time
beyond that required by the ATA-4 specification.
All ATA transfers are programmed in terms of system clock cycles (IP bus clocks) in the ATA Host
Controller timing registers. This puts constraints on the ATA protocols and their respective timing modes in
which the ATA Controller can communicate with the drive.
Faster ATA modes (i.e., UDMA 0, 1, 2) are supported when the system is running at a sufficient frequency
to provide adequate data transfer rates. Adequate data transfer rates are a function of the following:
The MPC5200 operating frequency (IP bus clock frequency)
Internal MPC5200 bus latencies
Other system load dependent variables
The ATA clock is the same frequency as the IP bus clock in MPC5200. See the MPC5200 User Manual [1].
NOTE:
All output timing numbers are specified for nominal 50 pF loads.
Table 26 PIO Mode Timing Specifications
PIO Timing Parameter
Min/Ma
x
(ns)
Mode 0
(ns)
Mode 1
(ns)
Mode 2
(ns)
Mode 3
(ns)
Mode 4
(ns)
SpecID
t0
Cycle Time
min
600
383
240
180
120
A8.1
t1
Address valid to DIOR/DIOW
setup
min
70
50
30
30
25
A8.2
t2
DIOR/DIOW pulse width 16-bit
8-bit
min
min
165
290
125
290
100
290
80
80
70
70
A8.3
t2i
DIOR/DIOW recovery time
min
—
—
—
70
25
A8.4
t3
DIOW data setup
min
60
45
30
30
20
A8.5
t4
DIOW data hold
min
30
20
15
10
10
A8.6
t5
DIOR data setup
min
50
35
20
20
20
A8.7
t6
DIOR data hold
min
5
5
5
5
5
A8.8
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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