參數(shù)資料
型號： MPC5200ID
廠商： Motorola, Inc.
英文描述： MPC5200 Hardware Specifications
中文描述： MPC5200的硬件規(guī)格
文件頁數(shù)： 27/76頁
文件大?。?/td> 1404K
代理商： MPC5200ID
MOTOROLA
MPC5200 Hardware Specifications
27
Electrical and Thermal Characteristics
NOTES:
1.
2.
Wait states for Reads and Writes can be specified as 0 to 127.
Dead cycles can be specified as 0 to 3. Dead cycles will be added to the end of Chip Select read access and will occur
in addition to any cycles which may already exist. These cycles provide a peripheral additional time to tri-state its bus
after a read operation. This is for all access types.
Transfer Size TSIZE(1:0) are available in Non-MUXed mode for MOST Graphics or Large Flash Modes only.
For understanding the different hold/valid/assertion/negation times refer to Figure 10.
The timing values in the above table are for a clock ratio of IP_CLK : PCI_CLK = 1 : 1 only.
The values will be different for other IP_CLK : PCI_CLK clock ratios.
3.
t
DV
PCI CLK to DATA output valid
-
2
ns
A7.3
t
DZ
PCI CLK to DATA output Hi Z
-
2
ns
A7.4
t
CSA
PCI CLK to CS assertion
-
1.8
ns
A7.5
t
CSN
PCI CLK to CS negation
-
1.8
ns
A7.6
t
OEA
PCI CLK to OE assertion
-
1.5
ns
A7.7
t
OEN
PCI CLK to OE negation
-
1.5
ns
A7.8
t
RWV
PCI CLK to RW valid
-
1
ns
A7.9
t
RWH
PCI CLK to RW hold
1
-
ns
A7.10
t
TSIZV
PCI CLK to TSIZ valid
-
2
ns
A7.11
t
TSIZH
PCI CLK to TSIZ hold
1
-
ns
A7.12
t
DS
DATA input to PCI CLK setup
2
-
ns
A7.13
t
DH
DATA input to PCI CLK hold
-
1
ns
A7.14
Table 24 Non-MUXed Mode Timing (continued)
Sym
Description
Min
Max
Units
Notes SpecID
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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