- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359188 > MPC5200B (飛思卡爾半導(dǎo)體(中國)有限公司) SDRAM/DDR Memory Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC5200B |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | SDRAM/DDR Memory Controller |
| 中文描述： | 內(nèi)存/ DDR存儲(chǔ)器控制器 |
| 文件頁數(shù)： | 14/78頁 |
| 文件大?。?/td> | 629K |
| 代理商： | MPC5200B |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁
MPC5200B Data Sheet, Rev. 1
Electrical and Thermal Characteristics
Freescale Semiconductor
14
3.2.4
e300 Core PLL Electrical Characteristics
The internal clocking of the e300 core is generated from and synchronized to the system clock by means
of a voltage-controlled core PLL.
3.3
AC Electrical Characteristics
Hyperlinks to the indicated timing specification sections are provided below.
Table 11. e300 PLL Specifications
Characteristic
Sym
Notes
Min
Typical
Max
Unit
SpecID
e300 frequency
f
core
(1)
NOTES:
1
The XLB_CLK frequency and e300 PLL Configuration bits must be chosen such that the resulting system
frequencies, CPU (core) frequency, and e300 PLL (VCO) frequency do not exceed their respective maximum or
minimum operating frequencies in
Table 12
.
2
This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different
types of jitter can exist on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is
rejected. Systemic jitter will be passed into and through the PLL to the internal clock circuitry.
3
Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required
for the PLL lock after a stable VDD and CORE_SYSCLK are reached during the power-on reset sequence. This
specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
50
—
550
MHz
O4.1
e300 cycle time
t
core
(1)
2.85
—
40.0
ns
O4.2
e300 VCO frequency
f
VCOcore
(1)
400
—
1200
MHz
O4.3
e300 input clock frequency
f
XLB_CLK
25
—
367
MHz
O4.4
e300 input clock cycle time
t
XLB_CLK
2.73
—
50.0
ns
O4.5
e300 input clock jitter
t
jitter
(2)
—
—
150
ps
O4.6
e300 PLL relock time
t
lock
(3)
—
—
100
μ
s
O4.7
AC Operating Frequency Data
USB
Clock AC Specifications
SPI
Resets
MSCAN
I
2
C
External Interrupts
SDRAM
J1850
PCI
PSC
Local Plus Bus
GPIOs and Timers
ATA
IEEE 1149.1 (JTAG) AC Specifications
Ethernet
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC5200 | Hardware Specifications |
| MPC5534 | Microcontroller |
| MPC7447A | PowerPC microprocessor |
| MPC7447ANXPNS | PowerPC microprocessor |
| MPC7455 | RISC Microprocessor Hardware Specifications |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC5200B_08 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SDRAM / DDR Memory Controller |
| MPC5200B_10 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SDRAM/DDR Memory Controller |
| MPC5200BDS | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Technical Data |
| MPC5200BV400 | 功能描述:微處理器 - MPU 400MHz 760MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC5200CBV266 | 功能描述:微處理器 - MPU 266MHz 760MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。