參數(shù)資料
型號： MPC5200B
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： SDRAM/DDR Memory Controller
中文描述： 內(nèi)存/ DDR存儲器控制器
文件頁數(shù)： 13/78頁
文件大?。?/td> 629K
代理商： MPC5200B
Electrical and Thermal Characteristics
MPC5200B Data Sheet, Rev. 1
Freescale Semiconductor
13
The MPC5200B clock generation uses two phase locked loop (PLL) blocks.
The system PLL (SYS_PLL) takes an external reference frequency and generates the internal
system clock. The system clock frequency is determined by the external reference frequency and
the settings of the SYS_PLL configuration.
The e300 core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry. The e300
core clock frequency is determined by the system clock frequency and the settings of the
CORE_PLL configuration.
3.2.1
System Oscillator Electrical Characteristics
3.2.2
RTC Oscillator Electrical Characteristics
3.2.3
System PLL Electrical Characteristics
Table 8. System Oscillator Electrical Characteristics
Characteristic
Sym
Notes
Min
Typical
Max
Unit
SpecID
SYS_XTAL frequency
f
sys_xtal
15.6
33.3
35.0
MHz
O1.1
Oscillator start-up time
t
up_osc
—
—
10
ms
O1.2
Table 9. RTC Oscillator Electrical Characteristics
Characteristic
Sym
Notes
Min
Typical
Max
Unit
SpecID
RTC_XTAL frequency
f
rtc_xtal
—
32.768
—
kHz
O2.1
Table 10. System PLL Specifications
Characteristic
Sym
Notes
Min
Typical
Max
Unit
SpecID
SYS_XTAL frequency
f
sys_xtal
(1)
NOTES:
1
The SYS_XTAL frequency and PLL Configuration bits must be chosen such that the resulting system frequency,
CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies.
2
This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different
types of jitter can exist on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is
rejected. Systemic jitter will be passed into and through the PLL to the internal clock circuitry.
3
Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required
for the PLL lock after a stable VDD and CORE_SYSCLKare reached during the power-on reset sequence. This
specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
15.6
33.3
35.0
MHz
O3.1
SYS_XTAL cycle time
t
sys_xtal
(1)
66.6
30.0
28.5
ns
O3.2
SYS_XTAL clock input jitter
t
jitter
(2)
—
—
150
ps
O3.3
System VCO frequency
f
VCOsys
(1)
250
533
800
MHz
O3.4
System PLL relock time
t
lock
(3)
—
—
100
μ
s
O3.5
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC5200B_08 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SDRAM / DDR Memory Controller
MPC5200B_10 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SDRAM/DDR Memory Controller
MPC5200BDS 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Technical Data
MPC5200BV400 功能描述:微處理器 - MPU 400MHz 760MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC5200CBV266 功能描述:微處理器 - MPU 266MHz 760MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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