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參數(shù)資料
| 型號： | MPC184VFB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 12/12頁 |
| 文件大小： | 0K |
| 描述： | IC SECURITY PROCESSOR 252-PBGA |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 處理器類型： | MPC1xx PowerPC ISA PCI 橋/存儲器 |
| 速度： | 66MHz |
| 電壓： | 1.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 252-BGA |
| 供應(yīng)商設(shè)備封裝： | 252-MAPBGA（21x21） |
| 包裝： | 托盤 |
MOTOROLA
MPC184 Security Processor Technical Summary
9
7.4 Advanced Encryption Standard Execution Unit (AESU)
The AESU is used to accelerate bulk data encryption/decryption in compliance with the Advanced
Encryption Standard algorith Rinjdael. The AESU executes on 128 bit blocks with a choice of key sizes:
128, 192, or 256 bits.
AESA is a symmetric key algorithm, the sender and receiver use the same key for both encryption and
decryption. The session key and IV(CBC mode) are supplied to the AESU module prior to encryption. The
processor supplies data to the module that is processed as 128 bit input. The AESU operates in ECB, CBC,
and counter modes.
7.5 Message Digest Execution Unit (MDEU) Module
The MDEU computes a single message digest (or hash or integrity check) value of all the data presented on
the input bus, using either the MD5, SHA-1 or SHA-256 algorithms for bulk data hashing. With any hash
algorithm, the larger message is mapped onto a smaller output space, therefore collisions are potential, albeit
not probable. The 160-bit hash value is a sufciently large space such that collisions are extremely rare. The
security of the hash function is based on the difculty of locating collisions. That is, it is computationally
infeasible to construct two distinct but similar messages that produce the same hash output.
SHA-1 is a 160 bit hash function, specied by the ANSI X9.30-2 and FIPS 180-1 standards.
The MD5 generates a 128 bit hash, and the algorithm is specied in RFC 1321.
The MDEU also supports HMAC computations, as specied in RFC 2104.
SHA-256 is a 256-bit hash function that provides 256 bits of security against collision attacks.
7.6
Random Number Generator (RNG)
The RNG is a digital integrated circuit capable of generating 32-bit random numbers. It is designed to
comply with FIPS 140-1 standards for randomness and non-determinism.
Because many cryptographic algorithms use random numbers as a source for generating a secret value (a
nonce), it is desirable to have a private RNG for use by the MPC184. The anonymity of each random number
must be maintained, as well as the unpredictability of the next random number. The FIPS-140 compliant
private RNG allows the system to develop random challenges or random secret keys. The secret key can thus
remain hidden from even the high-level application code, providing an added measure of physical security.
7.7 8KB General Purpose RAM (gpRAM)
The MPC184 contains 8KB of internal general purpose RAM that can be used to store keys, IV’s and data.
The internal scratchpad allows the user to store frequently used context on chip which increases system
performance by minimizing setup time. This feature is especially important when dealing with small
packets and in systems where bus bandwidth is limited.
8 Performance Estimates
Bulk encryption/authentication performance estimates shown in Table 8-1. include data/key/context reads
(from memory to MPC184), security processing (internal to MPC184), and writes of completed
data/context to memory by MPC184, using typical bus overhead.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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