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參數(shù)資料
| 型號： | MPC106ARX83TG |
| 廠商： | MOTOROLA INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI Bridge/Memory Controller |
| 中文描述： | PCI BUS CONTROLLER, CBGA304 |
| 封裝： | 21 X 25 MM, 3.16 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-304 |
| 文件頁數(shù)： | 2/28頁 |
| 文件大小： | 158K |
| 代理商： | MPC106ARX83TG |
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MPC106 PCI Bridge/Memory Controller Hardware Specifications
Overview
In this document, the term ‘60x’ is used to denote a 32-bit microprocessor from the PowerPC architecture
family that conforms to the bus interface of the PowerPC 601, PowerPC 603, or PowerPC 604
microprocessors. Note that this does not include the PowerPC 602 microprocessor which has a
multiplexed address/data bus. 60x processors implement the PowerPC architecture as it is specified for
32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32
bits, and floating-point data types of 32 and 64 bits (single-precision and double-precision).
To locate any published errata or updates for this document, refer to the website at
http://www.mot.com/SPS/PowerPC/.
1.1 Overview
The MPC106 provides an integrated high-bandwidth, high-performance, TTL-compatible interface
between a 60x processor, a secondary (L2) cache or additional (up to four total) 60x processors, the PCI
bus, and main memory. This section provides a block diagram showing the major functional units of the
106 and describes briefly how those units interact.
Figure 1 shows the major functional units within the 106. Note that this is a conceptual block diagram
intended to show the basic features rather than how these features are physically implemented on the
device.
Figure 1. Block Diagram
Target
Master
PCI Interface
PCI Bus
Memory
Interface
Power Management
Error/Interrupt
Control
Configuration
Registers
L2
60x Processor
Interface
L2 Cache
Interface
60x Bus
Memory
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