參數(shù)資料
型號: MPC2003SG50
廠商: MOTOROLA INC
元件分類: SRAM
英文描述: 256KB and 512KB BurstRAM Secondary Cache Module for PowerPC - Based Systems
中文描述: 128K X 36 CACHE SRAM MODULE, 14 ns, DMA136
封裝: DIMM-136
文件頁數(shù): 1/14頁
文件大?。?/td> 234K
代理商: MPC2003SG50
MPC2002
MPC2003
1
Motorola, Inc. 1995
256KB and 512KB BurstRAM
Secondary Cache Module for
PowerPC
– Based Systems
The MPC2002SG and MPC2003SG are designed to provide a burstable, high
performance, 256K/512K L2 cache for the PowerPC 60x processors. The mod-
ules are configured as 32K x 72 and 64K x 72 bits in a 136 pin dual readout single
inline memory module (DIMM). The module uses four of Motorola’s
MCM67M518 or MCM67M618 BiCMOS BurstRAMs.
Bursts can be initiated with either transfer start processor (TSP) or transfer
start controller (TSC). Subsequent burst addresses are generated internal to the
BurstRAM by the burst address advance (BAA) pin.
Write cycles are internally self timed and are initiated by the rising edge of the
clock (K) input. Eight write enables are provided for byte write control.
The cache family is designed to interface with the PowerPC 60x bus and re-
quires external tag.
PD0 – PD2 are reserved for density and speed identification.
PowerPC–style Burst Counter on Board
Dual Readout SIMM for Circuit Density
Single 5 V
±
5% Power Supply
All Inputs and Outputs are TTL Compatible
Three State Outputs
Byte Parity
Byte Write Capability
Fast Module Clock Rates: 66 MHz, 60 MHz, 50MHz
Decoupling Capacitors for each Fast Static RAM
High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes
I/Os are 3.3 V Compatible
BurstRAM is a trademark of Motorola.
PowerPC and PowerPC 601 are trademarks of International Business Machines Corp.
Order this document
by MPC2002/D
SEMICONDUCTOR TECHNICAL DATA
MPC2002
MPC2003
(Formerly MCM72MS32/64)
136–LEAD DIMM
CASE 1104–01
TOP VIEW
68
35
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